CD54HC243 TI | Alldatasheet

Document overview

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Technical content

Features

  • Typical Propagation Delay (A to B, B to A) of 7ns at VCC = 5V, CL = 15pF, TA = 25oC
  • Three-State Outputs
  • Buffered Inputs
  • Fanout (Over Temperature Range)
  • Wide Operating Temperature Range . . . -55oC to 125oC
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤1µA at VOL, VOH Pinout CD54HC243, CD54HCT243 (CERDIP) CD74HC243, CD74HCT243 (PDIP, SOIC) TOP VIEW

Description

The ’HC243 and ’HCT243 silicon-gate CMOS three-state bidirectional noninverting buffers are intended for two-way asynchronous communication between data buses. They have high-drive-current outputs that enable high-speed oper- ation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits and have speeds comparable to low-power Schottky TTL circuits. They can drive 15 LSTTL loads. The states of the output-enable (OEB, OEA) inputs determine both the direction of flow (A to B, B to A), and the three-state mode. OEB NC GND VCC OEA NC

Ordering Information

TEMP. RANGE (oC) PACKAGE CD54HC243F3A -55 to 125

14 Ld CERDIP

-55 to 125 -55 to 125

14 Ld PDIP

-55 to 125

14 Ld SOIC

-55 to 125 -55 to 125 -55 to 125 -55 to 125 NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. November 1997 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs [ /Title (CD74 HCT24 CD74 HC243 CD74 HCT24 /Sub- ject (High Speed CMOS Logic Quad-

‘HC243, ‘HCT243 TRUTH TABLE CONTROL INPUTS HC, HCT243 SERIES DATA PORT STATUS OEB OEA An Bn H H O I L H Z Z H L Z Z L L I O H= High Voltage Level L= Low Voltage Level I= Input O= Output (Same Level as Input) Z= High Impedance To prevent excess currents in the High Z modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. DIRECTION SELECT LOGIC OEB OEA CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

DC Input Diode Current, IIK DC Output Diode Current, IOK DC Drain Current, per Output, IO DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC Input Rise and Fall Time Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITS VI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage VIH 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 4.2 4.2 4.2 V Low Level Input Voltage VIL 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 1.8 1.8 1.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 1.9 1.9 1.9 V -0.02 4.5 4.4 4.4 4.4 V -0.02 5.9 5.9 5.9 V High Level Output Voltage TTL Loads 4.5 3.98 3.84 3.7 V -7.8 5.48 5.34 5.2 V Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 0.1 0.1 0.1 V 0.02 4.5 0.1 0.1 0.1 V 0.02 0.1 0.1 0.1 V Low Level Output Voltage TTL Loads 4.5 0.26 0.33 0.4 V 7.8 0.26 0.33 0.4 V CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

±0.1 µA Quiescent Device Current ICC VCC or GND 160 µA Three-State Leakage Current IOZ VIL or VIH ±0.5 ±0.5 ±10 µA HCT TYPES High Level Input Voltage VIH 4.5 to 5.5 V Low Level Input Voltage VIL 4.5 to 5.5 0.8 0.8 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 4.4 4.4 V High Level Output Voltage TTL Loads 4.5 3.98 3.84 3.7 V Low Level Output Voltage CMOS Loads VOL VIH or VIL 0.02 4.5 0.1 0.1 0.1 V Low Level Output Voltage TTL Loads 4.5 0.26 0.33 0.4 V Input Leakage Current II VCC to GND 5.5 ±0.1 µA Quiescent Device Current ICC VCC or GND 5.5 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 2) VCC -2.1 4.5 to 5.5 100 360 450 490 µA Three-State Leakage Current IOZ VIL or VIH 5.5 ±0.5 ±5.0 ±10 µA NOTE: (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITS VI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS An, Bn 1.1 OEA, OEB 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITS TYP MAX MAX MAX HC TYPES Propagation Delay Data to Outputs tPLH, tPHL CL = 50pF 115 135 ns 4.5 ns CL = 15pF ns CL = 50pF ns Output High-Z, to High Level to Low Level tPZL, tPZH CL = 50pF 150 190 225 ns CL = 50pF 4.5 ns CL = 15pF ns CL = 50pF ns Output High Level, Output Low Level to High-Z tPHZ, tPLZ CL = 50pF 150 190 225 ns CL = 50pF 4.5 ns CL = 15pF ns CL = 50pF ns Output Transition Times tTLH, tTHL CL = 50pF ns 4.5 ns ns Input Capacitance CI pF Three-State Output Capacitance CO pF Power Dissipation Capacitance (Notes 3, 4) CPD pF HCT TYPES Propagation Delay Data to Outputs tPLH, tPHL CL = 50pF 4.5 ns CL = 15pF ns Output High-Z to High Level to Low Level tPZH, tPZL CL = 50pF 4.5 ns CL = 15pF ns Output High Level, Output Low Level to High-Z tPHZ, tPLZ CL = 50pF 4.5 ns CL = 15pF ns Output Transition Times tTLH, tTHL CL = 50pF 4.5 ns Input Capacitance CI pF Three-State Output Capacitance CO pF Power Dissipation Capacitance (Notes 3, 4) CPD pF NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CD54HC243, CD74HC243, CD54HCT243, CD74HCT243

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) 8409001CA ACTIVE CDIP J TBD Call TI N / A for Pkg Type CD54HC243F ACTIVE CDIP J TBD Call TI N / A for Pkg Type CD54HC243F3A ACTIVE CDIP J TBD Call TI N / A for Pkg Type CD54HCT243F3A ACTIVE CDIP J TBD Call TI N / A for Pkg Type CD74HC243E ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC243EE4 ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC243M ACTIVE SOIC D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC243M96 ACTIVE SOIC D 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC243M96E4 ACTIVE SOIC D 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC243ME4 ACTIVE SOIC D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC243MT ACTIVE SOIC D 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC243MTE4 ACTIVE SOIC D 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT243E ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT243EE4 ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT243M ACTIVE SOIC D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT243ME4 ACTIVE SOIC D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2006 Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2006 Addendum-Page 2

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