84088012A

SNJ54HC112 TI | Alldatasheet

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SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max description/ordering information The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

ORDERING INFORMATION

PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC112N SN74HC112N −40°C to 85°C Tube of 40 SN74HC112D −40°C to 85°C SOIC − D Reel of 2500 SN74HC112DR HC112 SOIC − D Reel of 250 SN74HC112DT HC112 CDIP − J Tube of 25 SNJ54HC112J SNJ54HC112J −55°C to 125°C CFP − W Tube of 150 SNJ54HC112W SNJ54HC112W −55 C to 125 C LCCC − FK Tube of 55 SNJ54HC112FK SNJ54HC112FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 20 19 9 10 11 12 13 2CLR 2CLK NC 1PRE NC 1CLK NC V 1CLR GND NC SN54HC112 . . . FK PACKAGE (TOP VIEW) CC NC − No internal connection 1CLK 1PRE GND VCC 1CLR 2CLR 2CLK 2PRE SN54HC112 . . . J OR W PACKAGE SN74HC112 . . . D OR N PACKAGE (TOP VIEW) 2PRE Copyright  2003, Texas Instruments Incorporated !"#$ % &'!!( $ #% )'*+ &#$ ,#$(- !,'&$% & !" $ %)(& &#$ (/#% %$!'"( %$# $1- !,'&$ )!&(%% 2 ,(% (&(%%#! &+',( $(%$ +(%% $.(!0 $(,- )!&(%% 2 ,(% (&(%%#! &+',( $(%$

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H H L L H H H L H L H H L H L H H H H H Toggle H H H X X † This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK J CLR Q Q C C C C K TG TG TG TG C C C C C C

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA Continuous output current, IO (VO = 0 to VCC) ±25 mA Continuous current through VCC or GND ±50 mA Package thermal impedance, θJA (see Note 2): D package 73°C/W N package 67°C/W Storage temperature range, Tstg −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC112 SN74HC112 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VIL Low-level input voltage VCC = 6 V 1.8 1.8 V VI Input voltage VCC VCC V VO Output voltage VCC VCC V VCC = 2 V 1000 1000 tt‡ Input transition (rise and fall) time VCC = 4.5 V 500 500 ns tt‡ Input transition (rise and fall) time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC112 SN74HC112 UNIT PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 V VOH VI = VIH or VIL IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 V IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 V VOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 V IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V µA Ci

2 V to 6 V

timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC112 SN74HC112 UNIT VCC MIN MAX MIN MAX MIN MAX UNIT 2 V 3.4 fclock Clock frequency 4.5 V MHz fclock Clock frequency 6 V MHz 2 V 100 150 125 PRE or CLR low 4.5 V tw Pulse duration PRE or CLR low 6 V ns tw Pulse duration 2 V 100 150 125 ns CLK high or low 4.5 V CLK high or low 6 V 2 V 100 150 125 Data (J, K) 4.5 V tsu Setup time before CLK↓ Data (J, K) 6 V ns tsu Setup time before CLK↓ 2 V 100 150 125 ns PRE or CLR inactive 4.5 V PRE or CLR inactive 6 V 2 V th Hold time, data after CLK↓ 4.5 V ns th Hold time, data after CLK↓ 6 V ns

SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC112 SN74HC112 UNIT PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 3.4 fmax 4.5 V MHz fmax 6 V MHz 2 V 165 245 205 PRE or CLR Q or Q 4.5 V tpd PRE or CLR Q or Q 6 V ns tpd 2 V 125 185 155 ns CLK Q or Q 4.5 V CLK Q or Q 6 V 2 V 110 tt Q or Q 4.5 V ns tt Q or Q 6 V ns operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load pF

CL includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) 84088012A ACTIVE LCCC FK None Call TI Level-NC-NC-NC 8408801EA ACTIVE CDIP J None Call TI Level-NC-NC-NC 8408801FA ACTIVE CFP W None Call TI Level-NC-NC-NC JM38510/65305BEA ACTIVE CDIP J None Call TI Level-NC-NC-NC SN54HC112J ACTIVE CDIP J None Call TI Level-NC-NC-NC SN74HC112D ACTIVE SOIC D Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC112DR ACTIVE SOIC D 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC112DT ACTIVE SOIC D 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC112N ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74HC112N3 OBSOLETE PDIP N None Call TI Call TI SNJ54HC112FK ACTIVE LCCC FK None Call TI Level-NC-NC-NC SNJ54HC112J ACTIVE CDIP J None Call TI Level-NC-NC-NC SNJ54HC112W ACTIVE CFP W None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) A NO. OF MIN MAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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