84074012A

SNJ54HC240 TI | Alldatasheet

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SCLS128D − DECEMBER 1982 − REVISED AUGUST 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Wide Operating Voltage Range of 2 V to 6 V High-Current Outputs Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 9 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 20 19 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 SN54HC240 . . . FK PACKAGE (TOP VIEW) 2Y4 1A1 1OE 1Y4 2A2 2OE 2Y1 GND 2A1 VCC description/ordering information These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 20 SN74HC240N SN74HC240N SOIC − DW Tube of 25 SN74HC240DW HC240 SOIC − DW Reel of 2000 SN74HC240DWR HC240 −40°C to 85°C SOP − NS Reel of 2000 SN74HC240NSR HC240 −40°C to 85°C SSOP − DB Reel of 2000 SN74HC240DBR HC240 Tube of 70 SN74HC240PW TSSOP − PW Reel of 2000 SN74HC240PWR HC240 TSSOP − PW Reel of 250 SN74HC240PWT HC240 CDIP − J Tube of 20 SNJ54HC240J SNJ54HC240J −55°C to 125°C CFP − W Tube of 85 SNJ54HC240W SNJ54HC240W −55 C to 125 C LCCC − FK Tube of 55 SNJ54HC240FK SNJ54HC240FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated !"# $ %&' # "$ (&)*%"# +"#', +&%#$ % ! # $('% %"# '."$ $#&!' $#" +"+ /"" #0, +&%# %'$$ 1 + '%'$$"*0 %*&+' #'$# +&%#$ % !(*" # # *'$$ #-'/$' #'+, "** #-' ( +&%#$ ( +&%# %'$$ 1 + '%'$$"*0

SCLS128D − DECEMBER 1982 − REVISED AUGUST 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE (each buffer/driver) INPUTS OUTPUT OE A OUTPUT Y L H L L L H H X Z logic diagram (positive logic) 1A1 1A2 1A3 1A4 1Y1 2A1 2A2 2A3 2A4 2Y1 1Y2 1Y3 1Y4 2Y2 2Y3 2Y4 1OE 2OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA Continuous output current, IO (VO = 0 to VCC) ±35 mA Continuous current through VCC or GND ±70 mA Package thermal impedance, θJA (see Note 2): DB package 70°C/W DW package 58°C/W N package 69°C/W NS package 60°C/W PW package 83°C/W Storage temperature range, Tstg −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7.

SCLS128D − DECEMBER 1982 − REVISED AUGUST 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54HC240 SN74HC240 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VIL Low-level input voltage VCC = 6 V 1.8 1.8 V VI Input voltage VCC VCC V VO Output voltage VCC VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns ∆t/∆v Input transition rise/fall time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC240 SN74HC240 UNIT PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 IOH = −20 µA 4.5 V 4.4 4.499 4.4 4.4 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 V VOH VI = VIH or VIL IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 V IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 V VOL VI = VIH or VIL IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 V IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 µA ICC VI = VCC or 0, IO = 0 6 V 160 µA Ci

2 V to 6 V

SCLS128D − DECEMBER 1982 − REVISED AUGUST 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC240 SN74HC240 UNIT PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 100 150 125 tpd A Y 4.5 V ns tpd A Y 6 V ns 2 V 150 225 190 ten OE Y 4.5 V ns ten OE Y 6 V ns 2 V 150 225 190 tdis OE Y 4.5 V ns tdis OE Y 6 V ns 2 V tt Y 4.5 V ns tt Y 6 V ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC240 SN74HC240 UNIT PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 150 225 190 tpd A Y 4.5 V ns tpd A Y 6 V ns 2 V 100 200 300 250 ten OE Y 4.5 V ns ten OE Y 6 V ns 2 V 210 315 265 tt Y 4.5 V ns tt Y 6 V ns operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per buffer/driver No load pF

CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. The outputs are measured one at a time with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) 84074012A ACTIVE LCCC FK None Call TI Level-NC-NC-NC 8407401RA ACTIVE CDIP J None Call TI Level-NC-NC-NC 8407401SA ACTIVE CFP W None Call TI Level-NC-NC-NC JM38510/65703B2A ACTIVE LCCC FK None Call TI Level-NC-NC-NC JM38510/65703BRA ACTIVE CDIP J None Call TI Level-NC-NC-NC SN54HC240J ACTIVE CDIP J None Call TI Level-NC-NC-NC SN74HC240DW ACTIVE SOIC DW Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74HC240DWR ACTIVE SOIC DW 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74HC240N ACTIVE PDIP N Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74HC240N3 OBSOLETE PDIP N None Call TI Call TI SN74HC240NSR ACTIVE SO NS 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC240PW ACTIVE TSSOP PW Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC240PWR ACTIVE TSSOP PW 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC240PWT ACTIVE TSSOP PW 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SNJ54HC240FK ACTIVE LCCC FK None Call TI Level-NC-NC-NC SNJ54HC240J ACTIVE CDIP J None Call TI Level-NC-NC-NC SNJ54HC240W ACTIVE CFP W None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) A NO. OF MIN MAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M 0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

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