84073012A

SN54HC174_16 TI1 | Alldatasheet

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Technical content

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0055/C0052 /C0072/C0069/C0088 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Wide Operating Voltage Range of 2 V to 6 V /C0068Outputs Can Drive Up To 10 LSTTL Loads /C0068Low Power Consumption, 80-µA Max ICC /C0068Typical tpd = 14 ns /C0068±4-mA Output Drive at 5 V /C0068Low Input Current of 1 µA Max /C0068Contain Six Flip-Flops With Single-Rail Outputs /C0068Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators description/ordering information These positive-edge-triggered D-type flip-flops have a direct clear (CLR ) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

ORDERING INFORMATION

TA PACKAGE † PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC174N SN74HC174N Tube of 40 SN74HC174D SOIC − D Reel of 2500 SN74HC174DR HC174SOIC − D Reel of 250 SN74HC174DT HC174 −40°C to 85°C SOP − NS Reel of 2000 SN74HC174NSR HC174−40 C to 85C SSOP − DB Reel of 2000 SN74HC174DBR HC174 Tube of 90 SN74HC174PW TSSOP − PW Reel of 2000 SN74HC174PWR HC174TSSOP − PW Reel of 250 SN74HC174PWT HC174 CDIP − J Tube of 25 SNJ54HC174J SNJ54HC174J −55°C to 125°C CFP − W Tube of 150 SNJ54HC174W SNJ54HC174W−55 C to 125C LCCC − FK Tube of 55 SNJ54HC174FK SNJ54HC174FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SN54HC174 ...J O R W PACKAGE SN74HC174 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 3212 0 1 9 91 0 1 1 1 2 1 3 NC NC SN54HC17 4...F K PACKAGE (TOP VIEW)1Q CLR NC CLK 4Q 6Q GND NC VCC CLR GND V CC CLK NC − No internal connection Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0055/C0052 /C0072/C0069/C0088 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(each flip-flop) INPUTS OUTPUT CLR CLK D OUTPUT Q L X X L H ↑ HH H ↑ LL H L X Q 0 logic diagram (positive logic) R To Five Other Channels CLR CLK Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0055/C0052 /C0072/C0069/C0088 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54HC174 SN74HC174 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVIL Low-level input voltage VCC = 6 V 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns∆t/∆v Input transition rise/fall time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC174 SN74HC174 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 VVOH VI = VIH or VIL V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA C i 2 V to 6 V 3 10 10 10 pF

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0055/C0052 /C0072/C0069/C0088 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC174 SN74HC174 UNITVCC MIN MAX MIN MAX MIN MAX UNIT 2 V 6 4.2 5 fclock Clock frequency 4.5 V 31 21 25 MHzfclock Clock frequency

6 V 36 25 29

2 V 80 120 100

CLR low 4.5 V 16 24 20 tw Pulse duration CLR low

6 V 14 20 17

nstw Pulse duration 2 V 80 120 100 ns CLK high or low 4.5 V 16 24 20CLK high or low

2 V 100 150 125

Data 4.5 V 20 30 25 tsu Setup time before CLK↑ Data

6 V 17 25 21

nstsu Setup time before CLK↑ 2 V 100 150 125 ns CLR inactive 4.5 V 20 30 25CLR inactive

2 V 0 0 0

th Hold time, data after CLK↑ 4.5 V 0 0 0 nsth Hold time, data after CLK

6 V 0 0 0

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC174 SN74HC174 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 6 9 4.2 5 fmax 4.5 V 31 44 21 25 MHzfmax

6 V 36 50 25 29

2 V 58 160 240 200

CLR Any 4.5 V 17 32 48 40 tpd CLR Any

6 V 14 27 41 34

nstpd 2 V 58 160 240 200 ns CLK Any 4.5 V 17 32 48 40CLK Any

2 V 38 75 110 90

tt Any 4.5 V 8 15 22 19 nstt Any

6 V 6 13 19 16

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per flip-flop No load 27 pF

NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

www.ti.com 17-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 84073012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84073012A SNJ54HC 174FK 8407301EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407301EA SNJ54HC174J 8407301FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407301FA SNJ54HC174W JM38510/65307BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65307BEA M38510/65307BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65307BEA SN54HC174J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC174J SN74HC174D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC174N SN74HC174NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC174N SN74HC174NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174

www.ti.com 17-Dec-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC174PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SN74HC174PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC174 SNJ54HC174FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84073012A SNJ54HC 174FK SNJ54HC174J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407301EA SNJ54HC174J SNJ54HC174W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8407301FA SNJ54HC174W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 17-Dec-2015 Addendum-Page 3 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC174, SN54HC174-SP, SN74HC174 :

• Catalog: SN74HC174 , SN54HC174
• Military: SN54HC174
• Space: SN54HC174-SP NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC174DBR SSOP DB 16 2000 367.0 367.0 38.0 SN74HC174DR SOIC D 16 2500 364.0 364.0 27.0 SN74HC174DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC174DRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74HC174NSR SO NS 16 2000 367.0 367.0 38.0 SN74HC174PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74HC174PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC174PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC174PWT TSSOP PW 16 250 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2016 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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