CD54HC75 TI | Alldatasheet

Document overview

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Technical content

Features

  • True and Complementary Outputs
  • Buffered Inputs and Outputs
  • Fanout (Over Temperature Range)
  • Wide Operating Temperature Range . . . -55 oC to 125oC
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH

Description

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs ( 1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input ( 1E and2E) is LOW the output is not affected. Pinout CD54HC75, CD54HCT75 (CERDIP) CD74HC75 (PDIP, SOIC, SOP, TSSOP) CD74HCT75 (PDIP, SOIC, TSSOP) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE CD54HC75F3A -55 to 125 16 Ld CERDIP CD54HCT75F3A -55 to 125 16 Ld CERDIP CD74HC75E -55 to 125 16 Ld PDIP CD74HC75M -55 to 125 16 Ld SOIC CD74HC75MT -55 to 125 16 Ld SOIC CD74HC75M96 -55 to 125 16 Ld SOIC CD74HC75NSR -55 to 125 16 Ld SOP CD74HC75PW -55 to 125 16 Ld TSSOP CD74HC75PWR -55 to 125 16 Ld TSSOP CD74HCT75E -55 to 125 16 Ld PDIP CD74HCT75M -55 to 125 16 Ld SOIC CD74HCT75PWT -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 1Q0 1D0 1D1 VCC 2D0 2Q1 2D1 1Q0 1Q1 GND 2Q0 2Q0 2Q1 1Q1 March 1998 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 Dual 2-Bit Bistable Transparent Latch [ /Title (CD74 H C75, C D74 H CT75 /Sub- ject (Dual 2-Bit B istabl e

1 OF 2

FIGURE 1. LOGIC DIAGRAM FIGURE 2. LATCH DETAIL

12 GND

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Drain Current, per Output, IO DC Output Diode Current, IOK DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time Package Thermal Impedance,θ JA (see Note 1) Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage CMOS Loads V OH VIH or VIL High Level Output Voltage TTL Loads -- - - - ---- V Low Level Output Voltage CMOS Loads V OL VIH or VIL Low Level Output Voltage TTL Loads -- - - - ---- V Input Leakage Current I I VCC or GND CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

0 6 - - 4 - 40 - 80 µA HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage CMOS Loads V OH VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads V OL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current I I VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 4 - 40 - 80 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load CC (Note 2) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS D0, D1 0.8 1E,2E 1.2 NOTE: Unit Load is∆ICC limit specified in DC Electrical Specifica- tions table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Pulse Width Enable Input t W - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Setup Time D to Enable t SU - 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Hold Time Enable to D t H -2 3 - - 3 - 3 - n s 4.5 3 - - 3 - 3 - ns 6 3 - - 3-3- n s HCT TYPES Pulse Width Enable Input t W - 4.5 16 - - 20 - 24 - ns Setup Time D to Enable t SU - 4.5 12 - - 15 - 18 - ns Hold Time Enable to D t H - 4.5 3 - - 3 - 3 - ns Switching SpecificationsInput tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, Data to Q tPLH , tPHL C L = 50pF 2 - - 110 - 140 - 165 ns C L = 50pF 4.5 - - 22 - 28 - 33 ns C L = 50pF 6 - - 19 - 24 - 28 ns Propagation Delay, Data toQ tPLH , tPHL C L = 50pF 2 - - 130 - 165 - 195 ns C L = 50pF 4.5 - - 26 - 33 - 39 ns C L = 15pF 5 - 10 - ---- n s C L = 50pF 6 - - 22 - 28 - 33 ns Propagation Delay, Enable to Q tPLH , tPHL C L = 50pF 2 - - 130 - 165 - 195 ns C L = 50pF 4.5 - - 26 - 33 - 39 ns C L = 15pF 5 - 10 - ---- n s C L = 50pF 6 - - 22 - 28 - 33 ns Propagation Delay, Enable toQ tPLH , tPHL C L = 50pF 2 - - 130 - 165 - 195 ns C L = 50pF 4.5 - - 26 - 33 - 39 ns C L = 15pF 5 - 11 - ---- n s C L = 50pF 6 - - 22 - 28 - 33 ns Output Transition Time t TLH , tTHL C L = 50pF 2 - - 75 - 95 - 110 ns C L = 50pF 4.5 - - 15 - 19 - 22 ns C L = 50pF 6 - - 13 - 16 - 19 ns Input Capacitance C I - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, Data to Q tPLH , tPHL C L = 50pF 4.5 - - 28 - 35 - 42 ns C L = 15pF 5 - 11 - ---- n s Propagation Delay, Data toQ tPLH , tPHL C L = 50pF 4.5 - - 28 - 35 - 42 ns C L = 15pF 5 - 11 - ---- n s Propagation Delay, Enable to Q tPLH , tPHL C L = 50pF 4.5 - - 28 - 35 - 42 ns C L = 15pF 5 11 - ---- n s Prerequisite For Switching Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9075801MEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC 8407001EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HC75F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HCT75F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD74HC75E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC75M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC75PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT75E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT75M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT75ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2005 Addendum-Page 1

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2005 Addendum-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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