82C82 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Full Eight-Bit Parallel Latching Buffer
  • Bipolar 8282 Compatible
  • Three-State Noninverting Outputs
  • Gated Inputs: - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors
  • Single 5V Power Supply
  • Operating Temperature Ranges oC to +70oC

Description

The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this sig- nal. The active low output enable ( OE) permits simple inter- face to state-of-the-art microprocessor systems.

Ordering Information

PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CP82C82 0 oC to +70oC 20 Ld PDIP E20.3 IP82C82 -40 oC to +85oC CS82C82 0 oC to +70oC 20 Ld PLCC N20.35 IS82C82 -40 oC to +85oC CD82C82 0 oC to +70oC 20 Ld CERDIP F20.3 ID82C82 -40 oC to +85oC MD82C82/B -55 oC to +125oC 8406701RA SMD # MR82C82/B -55 oC to +125oC 20 Pad CLCC J20.A 84067012A SMD # Pinouts 82C82 (PDIP, CERDIP) TOP VIEW 82C82 (PLCC, CLCC) TOP VIEW 1DI0 DI1 DI2 DI3 DI4 DI5 DI7 DI6 OE GND VCC DO 1 DO 2 DO 3 DO 0 DO 4 DO 5 DO 6 DO 7 STB 193 2 201 9 10 11 12 13 DI4 DI5 DI6 DI7 DI3 OE GND STB DO 7 DO 6 DO 2 DO 3 DO 4 DO 5 DO 1 DI2 DI1 DI0 VCC DO 0 TRUTH TABLE STB OE DI DO X H X Hi-Z HL LL HL HH ↓ LX † H = Logic One L = Logic Zero X = Don’t Care † = Latched to Value of Last Data Hi-Z = High Impedance ↓ = Neg. Transition PIN NAMES PIN DESCRIPTION DI0-DI7 Data Input Pins DO 0-DO 7 Data Output Pins STB Active High Strobe OE Active Low Output Enable File Number 2975.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

and cause a disruption in device operation. to a valid logic level internal to the device. related to input transitioning is reduced by this factor also. FIGURE 16. 82C82/83H FIGURE 17. 82C86H/87H GATED INPUTS

Application Information

The transient current required to charge and discharge the 300pF load capacitance specified in the 82C82 data sheet is determined by: Assuming that all outputs change state at the same time and that dv/dt is constant; where tR = 20ns, V CC = 5.0V, CL = 300pF on each of eight outputs. This current spike may cause a large negative voltage spike on VCC , which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1µF ceramic disc decoupling capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. IC L= (dv/dt) (EQ. 1) IC L= (EQ. 2) V CC x 80%() I = 8 x 300 x 10-12() x (5.0V x 0.8)/ 20 x 109–() = 480mA (EQ. 4) FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA θJC oC to +150oC Maximum Junction Temperature (PLCC Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V C82C82, I82C82 (Note 1) 2.2 - V M82C82 (Note 1) VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage 2.9 - V I OH = -8mA,OE = GND VCC -0.4V - V I OH = -100µA,OE = GND VOL Logical Zero Output Voltage - 0.4 V I OL = 8mA,OE = GND II Input Leakage Current -1.0 1.0 µAV IN = GND or VCC , DIP Pins 1-9, 11 IO Output Leakage Current -10.0 10.0 µAV O = GND or VCC ,OE ≥ VCC -0.5V DIP Pins 12-19 ICCSB Standby Power Supply Cur- rent -1 0 µAV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz T A = +25oC, VCC = 5V, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIHmin to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (STB,OE) are tested separately with all device data input pins at VCC -0.4. Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C IN Input Capacitance 13 pF Freq = 1MHz, all measurements are referenced to device GND C OUT Output Capacitance 20 pF 82C82

C L = 300pF (Note 1), Freq = 1MHz TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (1) TIVOV Propagation Delay Input to Output - 35 ns Notes 2, 3 (2) TSHOV Propagation Delay STB to Output - 55 ns Notes 2, 3 (3) TEHOZ Output Disable Time - 35 ns Notes 2, 3 (4) TELOV Output Enable Time - 50 ns Notes 2, 3 (5) TIVSL Input to STB Setup Time 0 - ns Notes 2, 3 (6) TSLIX Input to STB Hold Time 25 - ns Notes 2, 3 (7) TSHSL STB High Time 25 - ns Notes 2, 3 (8) TR, TF Input Rise/Fall Times - 20 ns Notes 2, 3 NOTES: 1. Output load capacitance is rated at 300pF for ceramic and plastic packages. 2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V. 3. Input test signals must switch between V IL - 0.4V and VIH +0.4V. TR, TF (8) TIVSL (5) TSLIX (6) 2.0V 0.8V VOH -0.1V TELOV (4) VOL +0.1V 2.4V 0.8V TEHOZ (3) TSHSL (7) (1) TIVOV TSHOV (2) INPUTS STB OUTPUTS OE Test Load Circuits NOTE: Includes stray and jig capacitance. OUTPUT TEST 300pF 150Ω 1.7V POINT (NOTE) TIVOV, TSHOV, TELOV OUTPUT TEST 50pF 300Ω 0.6V POINT (NOTE) TEHOZ OUTPUT HIGH DISABLE OUTPUT TEST 50pF 300Ω 3.3V POINT (NOTE) TEHOZ OUTPUT LOW DISABLE 82C82

NOTES: 1. VCC = 5.5± 0.5V, GND = 0V. 2. VIH = 4.5V±10%. 3. VIL = -0.2V to 0.4V. 4. R1 = 47kΩ± 5%. 5. R2 = 2.0kΩ± 5%. 6. R3 = 4.2kΩ± 5%. 7. R4 = 470kΩ± 5%. 8. C1 = 0.01µF minimum. R 1F2 A R 2 VCC R 1F2 R 1F2 R 1F2 R 1 R 1 R 1 R 1 R 1 F0 R 1 A A A A A A A A VCC R 2 R 3 R 3 F2 VCC /2 10 11 12 139 321 2 0 1 9 R 3 VCC /2 R 3 VCC /2 R 3 VCC /2 R 3 VCC /2 R 3 VCC /2 R 3 R 3 R 3 R 3 R 3 R 3 R 3 R 3 R 3R 3R 3 F0 F1 V CC /2 VCC VCC /2 82C82

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 118.1 x 92.1 x 19±1mils METALLIZATION: Type: Si - Al Thickness: 11k Å ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: 2.00 x 105 A/cm2 Metallization Mask Layout 82C82 1 20 19 18 1414 121110 8 9 D11 D10 V CC DO0 D01 D12 D13 D14 D15 D16 D17 OE GND STB DO7 DO6 DO5 DO4 DO3 DO2 82C82