8405601CA

SN74HC74 TI | Alldatasheet

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Technical content

SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features

• Buffered inputs
• Wide operating voltage range: 2 V to 6 V
• Wide operating temperature range: -40°C to +85°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL logic ICs

2 Applications

• Convert a momentary switch to a toggle switch
• Divide a clock signal by 2 or 4

3 Description

The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC74D SOIC (14) 8.70 mm × 3.90 mm SN74HC74DB SSOP (14) 6.50 mm × 5.30 mm SN74HC74N PDIP (14) 19.30 mm × 6.40 mm SN74HC74NS SO (14) 10.20 mm × 5.30 mm SN74HC74PW TSSOP (14) 5.00 mm × 4.40 mm SN54HC74J CDIP (14) 21.30 mm × 7.60 mm SN54HC74W CFP (14) 9.20 mm × 6.29 mm SN54HC74FK LCCC (20) 8.90 mm × 8.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. xCLK C xD C C C C xQ C xPRE xQ xCLR C C C C Functional pinout SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2015) to Revision F (June 2021) Page

• RθJA increased for the D (86 to 133.6 ℃/W), DB (96 to 107.7 ℃/W), NS (76 to 122.6 ℃/W), and PW (113 to SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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5 Pin Configuration and Functions

D, DB, N, NS, PW, J, or W Package 14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP Top View 3 2 1 20 19 9 10 11 12 13 1CLK NC 1PRE NC 1CLRNC VCC 2CLR 1Q GND NC 2Q 2Q NC 2CLK NC 20-Pin LCCC Top View Pin Functions PIN I/O DESCRIPTION NAME D, DB, N, NS, PW, J, or W FK

1 CLR 1 2 Input Channel 1, Clear Input, Active Low

1D 2 3 Input Channel 1, Data Input 1CLK 3 4 Input Channel 1, Positive edge triggered clock input

1 PRE 4 6 Input Channel 1, Preset Input, Active Low

1Q 5 8 Output Channel 1, Output

1 Q 6 9 Output Channel 1, Inverted Output

GND 7 10 — Ground

2 Q 8 12 Output Channel 2, Inverted Output

2Q 9 13 Output Channel 2, Output

2 PRE 10 14 Input Channel 2, Preset Input, Active Low

2CLK 11 16 Input Channel 2, Positive edge triggered clock input 2D 12 18 Input Channel 2, Data Input

2 CLR 13 19 Input Channel 2, Clear Input, Active Low

VCC 14 20 — Positive Supply 17 — Not internally connected www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74HC74 SN54HC74

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 7 V IIK Input clamp current(2) VI < –0.5 V or VI > VCC ±20 mA IOK Output clamp current(2) VI < –0.5 V or VI > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature(3) 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) Guaranteed by design.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage 2 5 6 V VIH High-level input voltage VCC = 2 V 1.5 VVCC = 4.5 V 3.15 VCC = 6 V 4.2 VIL Low-level input voltage VCC = 2 V 0.5 VVCC = 4.5 V 1.35 VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V Δt/Δv Input transition rise and fall rate VCC = 2 V 1000 nsVCC = 4.5 V 500 VCC = 6 V 400 TA Operating free-air temperature SN54HC00 –55 125 SN74HC00 –40 85 SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) SN74HC74 SN54HC74 UNITD (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) J (CDIP) W (CFP) FK (LCCC)

14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 20 PINS

RθJA Junction-to-ambient Rθ JC(to Junction-to-case (top) RθJB Junction-to-board ΨJT Junction-to-top characterization parameter ΨJB Junction-to-board characterization parameter Rθ JC(bo Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics - 74

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT25°C -40°C to 85°C MIN TYP MAX MIN TYP MAX VOH High-level output voltage VI = VIH or VIL IOH = –20 µA 2 V 1.9 1.998 1.9 V 4.5 V 4.4 4.499 4.4 6 V 5.9 5.999 5.9 IOH = –4 mA 4.5 V 3.98 4.3 3.84 IOH = –5.2 mA 6 V 5.48 5.8 5.34 VOL Low-level output voltage VI = VIH or VIL IOL = 20 µA 2 V 0.002 0.1 0.1 V 4.5 V 0.001 0.1 0.1 6 V 0.001 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.33 II Input leakage current VI = VCC or 0 6 V ±0.1 ±1 µA ICC Supply current VI = VCC or 0 IO = 0 6 V 4 40 µA Ci Input capacitance 2 V to 6 V 3 10 10 pF www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74HC74 SN54HC74

6.6 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX VOH High-level output voltage VI = VIH or VIL IOH = -20 µA 2 V 1.9 1.998 1.9 1.9 V 6 V 5.9 5.999 5.9 5.9 IOH = -6 IOH = -7.8 mA 6 V 5.48 5.8 5.34 5.2 VOL Low-level output voltage VI = VIH or VIL IOL = 20 µA 2 V 0.002 0.1 0.1 0.1 V 6 V 0.001 0.1 0.1 0.1 IOL = 7.8 mA 6 V 0.15 0.26 0.33 0.4 II Input leakage current VI = VCC or 0 6 V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or

0 IO = 0 6 V 2 20 40 µA

2 V to

6 V 3 10 10 10 pF

6.7 Timing Requirements - 74

over operating free-air temperature range (unless otherwise noted) VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C MIN TYP MAX MIN TYP MAX fclock Clock frequency

2 V 6 5

MHz4.5 V 31 25

6 V 0 36 0 29

2 V 100 125

4.5 V 20 25

6 V 14 21

2 V 80 100

4.5 V 16 20

6 V 14 17

tsu Setup time before CLK↑ Data

6 V 17 21

2 V 25 30

4.5 V 5 6

6 V 4 5

th Hold time, data after CLK↑

2 V 0 0

ns4.5 V 0 0

6 V 0 0

SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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6.8 Timing Requirements - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX fclock Clock frequency 2 V 6 5 4.2 ns4.5 V 31 25 21

6 V 0 36 0 29 0 25

2 V 100 125 150

4.5 V 20 25 30

6 V 14 21 25

2 V 80 100 120

4.5 V 16 20 24

6 V 14 17 20

tsu Setup time before CLK↑ Data

6 V 17 21 25

2 V 25 30 40

4.5 V 5 6 8

6 V 4 5 7

th Hold time, data after CLK↑

2 V 0 0 0

MHz4.5 V 0 0 0

6 V 0 0 0

6.9 Switching Characteristics - 74

over operating free-air temperature range (unless otherwise noted) PARAMETER FROM TO VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C MIN TYP MAX MIN TYP MAX fmax

2 V 6 10 6

MHz4.5 V 31 50 25

6 V 36 60 29

2 V 70 230 290

4.5 V 20 46 58

6 V 15 39 49

2 V 70 175 220

4.5 V 20 35 44

6 V 15 30 39

2 V 28 75 95

ns4.5 V 8 15 19

6 V 6 13 16

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6.10 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER FROM TO VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX fmax 2 V 6 10 6 4.2 MHz4.5 V 31 50 25 21

6 V 36 60 29 25

2 V 70 230 290 345

4.5 V 20 46 58 69

6 V 15 39 49 59

2 V 70 175 220 250

4.5 V 20 35 44 50

6 V 15 30 39 42

2 V 28 75 95 110

ns4.5 V 8 15 19 22

6 V 6 13 16 19

6.11 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Cpd Power dissipation capacitance per gate No load 2 V to 6 V 35 pF

6.12 Typical Characteristics

TA = 25°C IOH Output High Current (mA) VOH Output High Voltage (V) 0 1 2 3 4 5 6 2-V 4.5-V 6-V Figure 6-1. Typical output voltage in the high state (VOH) IOL Output Low Current (mA) VOL Output Low Voltage (V) 0 1 2 3 4 5 6 0.05 0.1 0.15 0.2 0.25 0.3 2-V 4.5-V 6-V Figure 6-2. Typical output voltage in the low state (VOL) SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement. CL (1) From Output Under Test Test Point A. CL= 50 pF and includes probe and jig capacitance. Figure 7-1. Load Circuit VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% A. tt is the greater of tr and tf. Figure 7-2. Voltage Waveforms Transition Times Clock Input 50% VCC 0 V 50% 50% VCC 0 V tsu Data Input th Figure 7-3. Voltage Waveforms Setup and Hold Times 50% tw Input 50% VCC 0 V Figure 7-4. Voltage Waveforms Pulse Width 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% A. The maximum between tPLH and tPHL is used for tpd. Figure 7-5. Voltage Waveforms Propagation Delays www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74HC74 SN54HC74

8 Detailed Description

8.1 Overview

The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.

8.2 Functional Block Diagram

C C C C xQ C xPRE xQ xCLR C C C C

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times. The SN74HC74 can drive a load with a total capacitance less than or equal to the maximum load listed in the Section 6.9 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the Section 6.1.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Section 6.5. The worst case resistance is calculated with the maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section 6.5, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Section 6.3 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Section 6.1 table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND LogicInput Output VCCDevice -IIK +IIK +IOK -IOK Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74HC74 SN54HC74

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

Toggle switches are typically large, mechanically complex and relatively expensive. It is desirable to use a momentary switch instead because they are small, mechanically simple and low cost. Some systems require a toggle switch's functionality but are space or cost constrained and must use a momentary switch instead. If the data input (D) of the D-type flip-flop is tied to the inverted output ( Q), then each clock pulse will cause the value at the output (Q) to toggle. The momentary switch can be debounced and connected through a Schmitt-trigger buffer to the clock input (CLK) to toggle the output. This application also utilizes a power-on reset circuit to ensure that the output always starts in the LOW state when power is applied.

9.2 Typical Application

Q Q CLR Output PRE VCC VCC D CLK VCC Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Section 6.3. The supply voltage sets the device's electrical characteristics as described in the Section 6.5. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74HC74 plus the maximum supply current, I CC, listed in the Section 6.5. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Section 6.1. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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The maximum junction temperature, T J(max) listed in the Section 6.1, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either V CC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74HC74, as specified in the Section 6.5, and the desired input transition rate. A 10-k Ω resistor value is often used due to these factors. The SN74HC74 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section 6.3. Refer to the Section 8.3 for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Section 6.5. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Section 6.5. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Section 8.3 for additional information regarding the outputs for this device.

9.2.1.4 Timing Considerations

The SN74HC74 is a clocked device. As such, it requires special timing considerations to ensure normal operation. Primary timing factors to consider:

• Maximum clock frequency: the maximum operating clock frequency defined in Section 6.7 is the maximum frequency at which the device is guaranteed to function. This value refers specifically to the triggering waveform, measuring from one trigger level to the next.
• Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as defined in the Section 6.7.
• Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined in the Section 6.7.
• Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event, as defined in the Section 6.7.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC74 to the receiving device. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74HC74 SN54HC74

1. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation

9.2.3 Application Curves

Time (100 Ps/div) Voltage (2 V/div) D001 D001 Vout Vin Figure 9-2. Waveform for non-debounced switch. Time (200 ms/div) Voltage (2 V/div) D002 Vout Vin Figure 9-3. Waveform for debounced switch. SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Section 6.3. Each V CC terminal should have a bypass capacitor to prevent power disturbance. A 0.1- μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1- μF and 1- μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1. www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74HC74 SN54HC74

11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient.

11.2 Layout Example

0.1 F Unused input tied to GND Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Unused inputs tied to VCC Figure 11-1. Example layout for the SN74HC74 SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com SN74HC74, SN54HC74 SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74HC74 SN54HC74

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 5962-8405601VCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8405601VC A SNV54HC74J 5962-8405601VCA.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8405601VC A SNV54HC74J 5962-8405601VDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8405601VD A SNV54HC74W 5962-8405601VDA.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8405601VD A SNV54HC74W 84056012A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84056012A SNJ54HC 74FK 8405601CA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601CA SNJ54HC74J 8405601DA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601DA SNJ54HC74W JM38510/65302B2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302B2A JM38510/65302B2A.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302B2A JM38510/65302BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BCA JM38510/65302BCA.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BCA JM38510/65302BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BDA JM38510/65302BDA.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BDA M38510/65302B2A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302B2A Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) M38510/65302BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BCA M38510/65302BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 65302BDA SN54HC74J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC74J SN54HC74J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC74J SN74HC74D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC74 SN74HC74DBR Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DBR.A Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DBRG4 Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DR.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DRG4.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74DT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC74 SN74HC74DT.B Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC74 SN74HC74N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC74N SN74HC74N.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC74N SN74HC74NE4 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC74N SN74HC74NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74NSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74NSR.B Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74NSRG4 Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74NSRG4.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74PW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC74 SN74HC74PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74PWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74PWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74PWR1G4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Addendum-Page 2

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SN74HC74PWR1G4.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 SN74HC74PWT Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC74 SNJ54HC74FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84056012A SNJ54HC 74FK SNJ54HC74FK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84056012A SNJ54HC 74FK SNJ54HC74J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601CA SNJ54HC74J SNJ54HC74J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601CA SNJ54HC74J SNJ54HC74W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601DA SNJ54HC74W SNJ54HC74W.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8405601DA SNJ54HC74W (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 3

www.ti.com 7-Oct-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :

• Catalog : SN74HC74 , SN54HC74
• Automotive : SN74HC74-Q1 , SN74HC74-Q1
• Enhanced Product : SN74HC74-EP , SN74HC74-EP
• Military : SN54HC74
• Space : SN54HC74-SP NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC74DBR SSOP DB 14 2000 353.0 353.0 32.0 SN74HC74DR SOIC D 14 2500 340.5 336.1 32.0 SN74HC74DR SOIC D 14 2500 340.5 336.1 32.0 SN74HC74DRG4 SOIC D 14 2500 340.5 336.1 32.0 SN74HC74NSR SOP NS 14 2000 353.0 353.0 32.0 SN74HC74NSRG4 SOP NS 14 2000 353.0 353.0 32.0 SN74HC74PWR TSSOP PW 14 2000 356.0 356.0 35.0 SN74HC74PWR1G4 TSSOP PW 14 2000 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962-8405601VDA W CFP 14 25 506.98 26.16 6220 NA 5962-8405601VDA.A W CFP 14 25 506.98 26.16 6220 NA 84056012A FK LCCC 20 55 506.98 12.06 2030 NA 8405601DA W CFP 14 25 506.98 26.16 6220 NA JM38510/65302B2A FK LCCC 20 55 506.98 12.06 2030 NA JM38510/65302B2A.A FK LCCC 20 55 506.98 12.06 2030 NA JM38510/65302BDA W CFP 14 25 506.98 26.16 6220 NA JM38510/65302BDA.A W CFP 14 25 506.98 26.16 6220 NA M38510/65302B2A FK LCCC 20 55 506.98 12.06 2030 NA M38510/65302BDA W CFP 14 25 506.98 26.16 6220 NA SN74HC74N N PDIP 14 25 506 13.97 11230 4.32 SN74HC74N N PDIP 14 25 506 13.97 11230 4.32 SN74HC74N.A N PDIP 14 25 506 13.97 11230 4.32 SN74HC74N.A N PDIP 14 25 506 13.97 11230 4.32 SN74HC74NE4 N PDIP 14 25 506 13.97 11230 4.32 SN74HC74NE4 N PDIP 14 25 506 13.97 11230 4.32 SNJ54HC74FK FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC74FK.A FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC74W W CFP 14 25 506.98 26.16 6220 NA SNJ54HC74W.A W CFP 14 25 506.98 26.16 6220 NA Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.38 0.22 8.2

7.4 TYP

0.25 GAGE PLANE 0 -8

2 MAX

0.25 0.09 B 5.6 5.0 NOTE 4 A 6.5 5.9 NOTE 3 0.95 0.55 SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.85) 14X (0.45) 12X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.85) 14X (0.45) 12X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

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