84056012A

SN54HC74 TI | Alldatasheet

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SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Wide Operating Voltage Range of 2 V to 6 V /C0068 Outputs Can Drive Up To 10 LSTTL Loads /C0068 Low Power Consumption, 40-µA Max ICC /C0068 Typical tpd = 15 ns /C0068 ±4-mA Output Drive at 5 V /C0068 Low Input Current of 1 µA Max description/ordering information The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube of 25 SN74HC74N SN74HC74N Tube of 50 SN74HC74D SOIC – D Reel of 2500 SN74HC74DR HC74 Reel of 250 SN74HC74DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC74NSR HC74 SSOP – DB Reel of 2000 SN74HC74DBR HC74 Tube of 90 SN74HC74PW TSSOP – PW Reel of 2000 SN74HC74PWR HC74 Reel of 250 SN74HC74PWT CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J –55°C to 125°C CFP – W Tube of 150 SNJ54HC74W SNJ54HC74W LCCC – FK Tube of 55 SNJ54HC74FK SNJ54HC74FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 1CLR 1CLK 1PRE GND VCC 2CLR 2CLK 2PRE SN54HC74 ...J O R W PACKAGE SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 11 21 3 NC 2CLK NC 2PRE 1CLK NC 1PRE NC 1CLR NC V 2CLR GND NC SN54HC74 . . . FK PACKAGE (TOP VIEW) CC NC – No internal connection Copyright  2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

L LXX H † H † H H ↑ HH L H H ↑ LL H H H L X Q 0 Q 0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic diagram (positive logic) PRE CLK D CLR Q Q C C C C C C C C C C TG TG TG TG absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54HC74 SN74HC74 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC74 SN74HC74 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 4 80 40 µA C i 2 V to 6 V 3 10 10 10 pF

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC74 SN74HC74 UNITVCC MIN MAX MIN MAX MIN MAX UNIT 2 V 6 4.2 5 fclock Clock frequency 4.5 V 31 21 25 MHz

6 V 0 36 0 25 0 29

2 V 100 150 125

PRE or CLR low 4.5 V 20 30 25 t Pulse duration

6 V 17 25 21

2 V 80 120 100

CLK high or low 4.5 V 16 24 20

6 V 14 20 17

Data 4.5 V 20 30 25 t Setup time before CLK↑ nstsu Setup time before CLK ↑

2 V 25 40 30

PRE or CLR inactive 4.5 V 5 8 6

6 V 4 7 5

2 V 0 0 0

th Hold time, data after CLK↑ 4.5 V 0 0 0 ns

6 V 0 0 0

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC74 SN74HC74 UNITPARAMETER (INPUT) (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 6 10 4.2 5 fmax 4.5 V 31 50 21 25 MHz

6 V 36 60 25 29

2 V 70 230 345 290

PRE or CLR Q or Q 4.5 V 20 46 69 58 t d

6 V 15 39 59 49

CLK Q or Q 4.5 V 20 35 50 44

6 V 15 30 42 37

2 V 28 75 110 95

tt Q or Q 4.5 V 8 15 22 19 ns

6 V 6 13 19 16

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per flip-flop No load 35 pF

NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8405601VCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 5962-8405601VDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC 84056012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8405601CA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 8405601DA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/65302B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/65302BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/65302BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SN54HC74J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SN74HC74ADBLE OBSOLETE SSOP DB 14 None Call TI Call TI SN74HC74D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC74DBLE OBSOLETE SSOP DB 14 None Call TI Call TI SN74HC74DBR ACTIVE SSOP DB 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC74DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC74DT ACTIVE SOIC D 14 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC74N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74HC74N3 OBSOLETE PDIP N 14 None Call TI Call TI SN74HC74NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC74PW ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC74PWLE OBSOLETE TSSOP PW 14 None Call TI Call TI SN74HC74PWR ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC74PWT ACTIVE TSSOP PW 14 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SNJ54HC74FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54HC74J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SNJ54HC74W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 Addendum-Page 1

Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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