SN74HC86 TI | Alldatasheet
Document overview
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Technical content
SNx4HC86 Quadruple 2-Input XOR Gates
1 Features
- Buffered inputs
- Wide operating voltage range: 2 V to 6 V
- Wide operating temperature range: –40°C to +85°C
- Supports fanout up to 10 LSTTL loads
- Significant power reduction compared to LSTTL logic ICs
2 Applications
- Detect phase differences in input signals
- Create a selectable inverter / buffer
3 Description
This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC86D SOIC (14) 8.70 mm × 3.90 mm SN74HC86N PDIP (14) 19.30 mm × 6.40 mm SN74HC86NS SO (14) 10.20 mm × 5.30 mm SN74HC86PW TSSOP (14) 5.00 mm × 4.40 mm SN54HC86J CDIP (14) 21.30 mm × 7.60 mm SN54HC86W CFP (14) 9.20 mm × 6.29 mm SN54HC86FK LCCC (20) 8.90 mm × 8.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. GND VCC 1 1 Functional pinout www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: SN74HC86 SN54HC86 SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2003) to Revision F (April 2021) Page SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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5 Pin Configuration and Functions
Figure 5-1. D, N, NS, PW, J, or W Package 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP Top View 3 2 1 20 19 9 10 11 12 13 NC NC 1B 1A NC V CC 4B 2Y GND NC 3Y 3A NC NC 3B Figure 5-2. FK Package 20-Pin LCCC Top View Pin Functions PIN I/O DESCRIPTION NAME D, N, NS, PW, J, or W FK 1A 1 2 Input Channel 1, Input A 1B 2 3 Input Channel 1, Input B 1Y 3 4 Output Channel 1, Output Y 2A 4 6 Input Channel 2, Input A 2B 5 8 Input Channel 2, Input B 2Y 6 9 Output Channel 2, Output Y GND 7 10 — Ground 3Y 8 12 Output Channel 3, Output Y 3A 9 13 Input Channel 3, Input A 3B 10 14 Input Channel 3, Input B 4Y 11 16 Output Channel 4, Output Y 4A 12 18 Input Channel 4, Input A 4B 13 19 Input Channel 4, Input B VCC 14 20 — Positive Supply 17 — Not internally connected www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74HC86 SN54HC86
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 7 V IIK Input clamp current(2) VI < 0 V or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 V or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature(3) 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) Guaranteed by design.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage 2 5 6 V VIH High-level input voltage VCC = 2 V 1.5 VVCC = 4.5 V 3.15 VCC = 6 V 4.2 VIL Low-level input voltage VCC = 2 V 0.5 VVCC = 4.5 V 1.35 VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V Δt/Δv Input transition rise and fall rate VCC = 2 V 1000 nsVCC = 4.5 V 500 VCC = 6 V 400 TA Operating free-air temperature SN54HC86 –55 125 SN74HC86 –40 85
6.3 Thermal Information
THERMAL METRIC(1) SN74HC86 UNITD (SOIC) N (PDIP) NS (SOP) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 133.6 62.8 122.6 151.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.0 50.5 81.8 79.4 °C/W RθJB Junction-to-board thermal resistance 89.5 42.5 83.8 94.7 °C/W ΨJT Junction-to-top characterization parameter 45.5 30.1 45.4 25.2 °C/W SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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THERMAL METRIC(1) SN74HC86 UNITD (SOIC) N (PDIP) NS (SOP) PW (TSSOP) ΨJB Junction-to-board characterization parameter 89.1 42.3 83.4 94.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT25°C -40°C to 85°C MIN TYP MAX MIN TYP MAX VOH High-level output voltage VI = VIH or VIL IOH = -20 µA 2 V 1.9 1.998 1.9 V 4.5 V 4.4 4.499 4.4 6 V 5.9 5.999 5.9 IOH = -4 mA 4.5 V 3.98 4.3 3.84 IOH = -5.2 mA 6 V 5.48 5.8 5.34 VOL Low-level output voltage VI = VIH or VIL IOL = 20 µA 2 V 0.002 0.1 0.1 V 4.5 V 0.001 0.1 0.1 IOL = 20 µA 6 V 0.001 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.33 II Input leakage current VI = VCC or 0 6 V ±0.1 ±100 ±1000 nA ICC Supply current VI = VCC or 0 IO = 0 6 V 2 20 µA Ci Input capacitance 2 V to 6 V 3 10 10 pF
6.5 Electrical Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX VOH High-level output voltage VI = VIH or VIL IOH = –20 µA 2 V 1.9 1.998 1.9 1.9 V 6 V 5.9 5.999 5.9 5.9 IOH = –4 IOH = –5.2 mA 6 V 5.48 5.8 5.34 5.2 VOL Low-level output voltage VI = VIH or VIL IOL = 20 µA 2 V 0.002 0.1 0.1 0.1 V 6 V 0.001 0.1 0.1 0.1 IOL = 5.2 mA 6 V 0.15 0.26 0.33 0.4 www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74HC86 SN54HC86
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX II Input leakage current VI = VCC or 0 6 V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or 0 IO = 0 6 V 2 20 40 µA Ci Input capacitance
2 V to
6 V 3 10 10 10 pF
6.6 Switching Characteristics - 74
over operating free-air temperature range (unless otherwise noted) PARAMETER FROM TO VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C MIN TYP MAX MIN TYP MAX tpd Propagation delay A or B Y
2 V 40 100 125
ns4.5 V 12 20 25
6 V 10 17 21
2 V 28 75 95
ns4.5 V 8 15 19
6 V 6 13 16
6.7 Switching Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER FROM TO VCC Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay A or B Y
2 V 40 100 125 150
ns4.5 V 12 20 25 30
6 V 10 17 21 25
2 V 38 75 95 110
ns4.5 V 8 15 19 22
6 V 6 13 16 19
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Cpd Power dissipation capacitance per gate No load 2 V to 6 V 35 pF
6.9 Typical Characteristics
TA = 25°C SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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7 Parameter Measurement Information
- Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
- The outputs are measured one at a time, with one input transition per measurement. CL (1) From Output Under Test Test Point A. C L= 50 pF and includes probe and jig capacitance. Figure 7-1. Load Circuit VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% A. t t is the greater of tr and tf. Figure 7-2. Voltage Waveforms Transition Times 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% A. The maximum between t PLH and tPHL is used for tpd. Figure 7-3. Voltage Waveforms Propagation Delays SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. The SN74HC86 can drive a load with a total capacitance less than or equal to the maximum load listed in the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Electrical Characteristics - 74 . The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74HC86 SN54HC86
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. GND LogicInput Output VCCDevice -IIK +IIK +IOK -IOK Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table INPUTS OUTPUT A B Y L L L L H H H L H H H L SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
In this application, a 2-input XOR gate is used as a phase difference detector as shown in Figure 9-1 . The remaining three gates can be used for other applications in the system, or the inputs can be grounded and the channels left unused. The device is used to identify phase difference between a reference clock and another input clock. Whenever the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state. The output is fed into a low-pass filter to obtain a DC representation of the phase difference.
9.2 Typical Application
C R Output Input Clock Reference Clock Figure 9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74HC86 plus the maximum supply current, I CC, listed in the Electrical Characteristics - 74 . The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, T J(max) listed in the Absolute Maximum Ratings , is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Unused inputs must be terminated to either V CC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74HC86, as specified in the Electrical Characteristics - 74 , and the desired input transition rate. A 10-k Ω resistor value is often used due to these factors. www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74HC86 SN54HC86
The SN74HC86 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Recommended Operating Conditions. Refer to Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics - 74. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics - 74. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
- Add a decoupling capacitor from V CC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC86 to the receiving device. 3. Ensure the resistive load at the output is larger than (V CC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation
9.2.3 Application Curves
Figure 9-2. Typical application timing diagram SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1- μF and 1- μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient.
11.2 Layout Example
0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 11-1. Example layout for the SN74HC86 www.ti.com SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74HC86 SN54HC86
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- HCMOS Design Considerations
- CMOS Power Consumption and CPD Calculation
- Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74HC86, SN54HC86 SCLS100F – DECEMBER 1982 – REVISED APRIL 2021 www.ti.com
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www.ti.com 27-Oct-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 84046012A ACTIVE LCCC FK 20 55 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84046012A SNJ54HC 86FK Samples 8404601CA ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601CA SNJ54HC86J Samples 8404601DA ACTIVE CFP W 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601DA SNJ54HC86W Samples JM38510/65202BCA ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65202BCA Samples M38510/65202BCA ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65202BCA Samples SN54HC86J ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC86J Samples SN74HC86D OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC86 SN74HC86DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86DT OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HC86 SN74HC86N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC86N Samples SN74HC86NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC86N Samples SN74HC86NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HC86PW OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HC86 SN74HC86PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC86 Samples SN74HCS86DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCS86 Samples SNJ54HC86FK ACTIVE LCCC FK 20 55 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84046012A SNJ54HC 86FK Samples SNJ54HC86J ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601CA SNJ54HC86J Samples SNJ54HC86W ACTIVE CFP W 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404601DA SNJ54HC86W Samples Addendum-Page 1
www.ti.com 27-Oct-2024 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC86, SN74HC86 :
- Catalog : SN74HC86
- Automotive : SN74HC86-Q1 , SN74HC86-Q1
- Military : SN54HC86 Addendum-Page 2
www.ti.com 27-Oct-2024 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
- Military - QML certified for Military and Defense Applications Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 28-Oct-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SN74HCS86DYYR SOT-23- THIN Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 28-Oct-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC86DR SOIC D 14 2500 356.0 356.0 35.0 SN74HC86NSR SO NS 14 2000 356.0 356.0 35.0 SN74HC86PWR TSSOP PW 14 2000 356.0 356.0 35.0 SN74HCS86DYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 28-Oct-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 84046012A FK LCCC 20 55 506.98 12.06 2030 NA 8404601DA W CFP 14 25 506.98 26.16 6220 NA SN74HC86N N PDIP 14 25 506 13.97 11230 4.32 SN74HC86N N PDIP 14 25 506 13.97 11230 4.32 SN74HC86NE4 N PDIP 14 25 506 13.97 11230 4.32 SN74HC86NE4 N PDIP 14 25 506 13.97 11230 4.32 SNJ54HC86FK FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC86W W CFP 14 25 506.98 26.16 6220 NA Pack Materials-Page 3
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11
0.1 C A B
1.1 MAX
C SEATING PLANE 0.2
0.08 TYP
0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\
www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B
www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X
www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8
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