CD74HC30 TI | Alldatasheet

Document overview

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Technical content

Features

  • Buffered Inputs
  • Typical Propagation Delay: 10ns at VCC = 5V, C L = 15pF, TA = 25oC
  • Fanout (Over Temperature Range)
  • Wide Operating Temperature Range . . . -55 oC to 125oC
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH Pinout CD54HC30, CD54HCT30 (CERDIP) CD74HC30 (PDIP, SOIC, SOP, TSSOP) CD74HCT30 (PDIP, SOIC) TOP VIEW

Description

The ’HC30 and ’HCT30 eachcontain an 8-inputNAND gate in one package. They provide the system designer with the direct implementation of the positive logic 8-input NAND function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated cir- cuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. A B C D E F GND VCC NC H G NC NC Y

Ordering Information

TEMP. RANGE (oC) PACKAGE CD54HC30F3A -55 to 125 14 Ld CERDIP CD54HCT30F3A -55 to 125 14 Ld CERDIP CD74HC30E -55 to 125 14 Ld PDIP CD74HC30M -55 to 125 14 Ld SOIC CD74HC30MT -55 to 125 14 Ld SOIC CD74HC30M96 -55 to 125 14 Ld SOIC CD74HC30NSR -55 to 125 14 Ld SOP CD74HC30PW -55 to 125 14 Ld TSSOP CD74HC30PWR -55 to 125 14 Ld TSSOP CD74HC30PWT -55 to 125 14 Ld TSSOP CD74HCT30E -55 to 125 14 Ld PDIP CD74HCT30M -55 to 125 14 Ld SOIC CD74HCT30MT -55 to 125 14 Ld SOIC CD74HCT30M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated. CD54/74HC30, CD54/74HCT30 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CD54H C 30, C D74H C 30, C D74H C T30) /Subject (High Speed C MOS Logic 8- August 1997 - Revised September 2003

NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant A B C D E F G H Y Y = ABCDEFGH Y A B C D E F G H CD54/74HC30, CD54/74HCT30

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time Package Thermal Impedance,θ JA (see Note 1) Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO +85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage CMOS Loads V OH VIH or VIL High Level Output Voltage TTL Loads -- - - - ---- V Low Level Output Voltage CMOS Loads V OL VIH or VIL Low Level Output Voltage TTL Loads -- - - - ---- V Input Leakage Current I I VCC or GND CD54/74HC30, CD54/74HCT30

0 6 - - 2 - 20 - 40 µA HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage CMOS Loads V OH VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads V OL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current I I VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 2 - 20 - 40 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 2) CC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO +85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS All 0.6 NOTE: Unit Load is∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Switching SpecificationsInput tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay, Input to Output (Figure 1) tPLH , tPHL C L = 50pF 2 - - 130 - 165 - 195 ns 4.5 - - 26 - 33 - 39 ns 6 - - 22 - 28 - 33 ns Propagation Delay, Data Input to Output Y tPLH , tPHL C L = 15pF 5 - 10 - ---- n s CD54/74HC30, CD54/74HCT30

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8974601CA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 8404001CA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC CD54HC30F ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC CD54HC30F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC CD54HCT30F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC CD74HC30E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC30M ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC30M96 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC30MT ACTIVE SOIC D 14 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC30NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HC30PW ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HC30PWR ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HC30PWT ACTIVE TSSOP PW 14 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CD74HCT30E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT30M ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HCT30M96 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM CD74HCT30MT ACTIVE SOIC D 14 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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