8403A

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.

FEATURES

256-position variable resistance device Replaces 1, 2, or 4 potentiometers 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Power shutdown—less than 5 μA 3-wire,SPI-compatible serial data input

10 MHz update data loading rate

2.7 V to 5.5 V single-supply operation Qualified for automotive applications

APPLICATIONS

Mechanical potentiometer replacement Programmable filters, delays, time constants Volume control, panning Line impedance matching Power supply adjustment GENERAL DESCRIPTION The AD8400/AD8402/AD8403 provide a single-, dual-, or quad-channel, 256-position, digitally controlled variable resistor (VR) device.1 These devices perform the same electronic adjust- ment function as a mechanical potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SOIC-8 package. The AD8402 contains two independent variable resistors in space-saving SOIC-14 surface-mount packages. The AD8403 contains four independent variable resistors in 24-lead PDIP , SOIC, and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by the digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs, avoiding any make-before-break or break-before-make operation. (continued on Page 3) 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. FUNCTIONAL BLOCK DIAGRAM 88-BIT LATCH CK RS 88-BIT LATCH CK RS 88-BIT LATCH CK RS 88-BIT LATCH CK RS DAC SELECT A1, A0 10-BIT SERIAL LATCH CK RSQ D SDO SHDNRS AD8403 VDD DGND SDI CLK CS RDAC1 AGND1 RDAC2 AGND2 RDAC3 AGND3 RDAC4 AGND4SHDN SHDN SHDN SHDN 01092-001 Figure 1. CODE (Decimal) 100 0 64 128 192 255 RWA(D), RWB(D) (% of Nominal RAB) RWA RWB 01092-002 Figure 2. RWA and RWB vs. Code

Rev. E | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

7/10—Rev. D to Rev. E 10/05—Rev. C to Rev. D 11/01—Rev. B to Rev. C Edits to

Rev. E | Page 3 of 32 GENERAL DESCRIPTION (continued from Page 1) Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI- compatible, serial-to-parallel shift register that is loaded from a standard 3-wire, serial-input digital interface. Ten data bits make up the data-word clocked into the serial input register. The data-word is decoded where the first two bits determine the address of the VR latch to be loaded, and the last eight bits are the data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. The reset (RS ) pin forces the wiper to midscale by loading 80H into the VR latch. The SHDN pin forces the resistor to an end- to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. The AD8400 is available in the SOIC-8 surface mount. The AD8402 is available in both surface-mount (SOIC-14) and 14-lead PDIP packages, while the AD8403 is available in a narrow-body, 24-lead PDIP and a 24-lead, surface-mount package. The AD8402/AD8403 are also offered in the 1.1 mm thin TSSOP-14/TSSOP-24 packages for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C.

Rev. E | Page 4 of 32 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 KΩ VERSION VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V , −40°C ≤ TA ≤ +125°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB Resistor Nonlinearity2 R-INL RWB, VA = no connect −2 ±1/2 +2 LSB Nominal Resistance3 R AB T A = 25°C, model: AD840XYY10 8 10 12 kΩ Resistance Tempco ΔRAB/ΔT V AB = VDD, wiper = no connect 500 ppm/°C Wiper Resistance RW V DD = 5V, IW = VDD/RAB 50 100 Ω R W V DD = 3V, IW = VDD/RAB 200 Ω Nominal Resistance Match ΔR/RAB CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −2 ±1/2 +2 LSB Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB Voltage Divider Tempco ΔVW/ΔT Code = 80H 15 ppm/°C Full-Scale Error VWFSE Code = FFH −4 −2.8 0 LSB Zero-Scale Error VWZSE Code = 00H 0 1.3 2 LSB RESISTOR TERMINALS Voltage Range5 V A, B, W 0 VDD V Capacitance6 Ax, Capacitance Bx CA, B f = 1 MHz, measured to GND, code = 80H 75 pF Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 120 pF Shutdown Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH V DD = 5 V 2.4 V Input Logic Low VIL V DD = 5 V 0.8 V Input Logic High VIH V DD = 3 V 2.1 V Input Logic Low VIL V DD = 3 V 0.6 V Output Logic High VOH R L = 2.2 kΩ to VDD V DD − 0.1 V Output Logic Low VOL I OL = 1.6 mA, VDD = 5 V 0.4 V Input Current IIL V IN = 0 V or 5 V, VDD = 5 V ±1 μA Input Capacitance6 C IL 5 pF POWER SUPPLIES Power Supply Range VDD range 2.7 5.5 V Supply Current (CMOS) IDD V IH = VDD or VIL = 0 V 0.01 5 μA Supply Current (TTL) 8 I DD V IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA Power Dissipation (CMOS)9 P DISS V IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 μW Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/% PSS VDD = 3 V ± 10% 0.006 0.03 %/%

Rev. E | Page 5 of 32 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_10 K R = 10 kΩ 600 kHz Total Harmonic Distortion THDW V A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 % VW Settling Time tS V A = VDD, VB = 0 V, ±1% error band 2 μs Resistor Noise Voltage eNWB RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz Crosstalk11 C T V A = VDD, VB = 0 V −65 dB 1 Typical represents average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Rev. E | Page 6 of 32 ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V , −40°C ≤ TA ≤ +125°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL RWB, VA = No Connect −1 ±1/4 +1 LSB Resistor Nonlinearity2 R-INL RWB, VA = No Connect −2 ±1/2 +2 LSB Nominal Resistance3 R AB T A = 25°C, Model: AD840XYY50 35 50 65 kΩ R AB T A = 25°C, Model: AD840XYY100 70 100 130 kΩ Resistance Tempco ΔRAB/ΔT V AB = VDD, Wiper = No Connect 500 ppm/°C Wiper Resistance RW V DD = 5V, IW = VDD/RAB 50 100 Ω R W V DD = 3V, IW = VDD/RAB 200 Ω Nominal Resistance Match ΔR/RAB CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −4 ±1 +4 LSB Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB Voltage Divider Tempco ΔVW/ΔT Code = 80H 15 ppm/°C Full-Scale Error VWFSE Code = FFH −1 −0.25 0 LSB Zero-Scale Error VWZSE Code = 00H 0 +0.1 +1 LSB RESISTOR TERMINALS Voltage Range5 V A, VB, VW 0 VDD V Capacitance6 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = 80H 15 pF Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 80 pF Shutdown Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH V DD = 5 V 2.4 V Input Logic Low VIL V DD = 5 V 0.8 V Input Logic High VIH V DD = 3 V 2.1 V Input Logic Low VIL V DD = 3 V 0.6 V Output Logic High VOH R L = 2.2 kΩ to VDD V DD − 0.1 V Output Logic Low VOL I OL = 1.6 mA, VDD = 5 V 0.4 V Input Current IIL V IN = 0 V or 5 V, VDD = 5 V ±1 μA Input Capacitance6 C IL 5 pF POWER SUPPLIES Power Supply Range VDD range 2.7 5.5 V Supply Current (CMOS) IDD V IH = VDD or VIL = 0 V 0.01 5 μA Supply Current (TTL) 8 I DD V IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA Power Dissipation (CMOS)9 P DISS V IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 μW Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/% PSS VDD = 3 V ± 10% 0.006 0.03 %/%

Rev. E | Page 7 of 32 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_50 K R = 50 kΩ 125 kHz BW_100 K R = 100 kΩ 71 kHz Total Harmonic Distortion THDW V A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 % VW Settling Time tS_50 K VA = VDD, VB = 0 V, ±1% error band 9 μs t S_100 K VA = VDD, VB = 0 V, ±1% error band 18 μs Resistor Noise Voltage eNWB_50 K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz e NWB_100 K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz Crosstalk11 C T V A = VDD, VB = 0 V −65 dB 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Rev. E | Page 8 of 32 ELECTRICAL CHARACTERISTICS—1 KΩ VERSION VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V , −40°C ≤ TA ≤ +125°C, unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL RWB, VA = no connect −5 −1 +3 LSB Resistor Nonlinearity2 R-INL RWB, VA = no connect −4 ±1.5 +4 LSB Nominal Resistance3 R AB T A = 25°C, model: AD840XYY1 0.8 1.2 1.6 kΩ Resistance Tempco ΔRAB/ΔT V AB = VDD, wiper = no connect 700 ppm/°C Wiper Resistance RW V DD = 5V, IW = VDD/RAB 53 100 Ω R W V DD = 3V, IW = VDD/RAB 200 Ω Nominal Resistance Match ΔR/RAB CH 1 to CH 2, VAB = VDD, TA = 25°C 0.75 2 % DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −6 ±2 +6 LSB Differential Nonlinearity4 DNL VDD = 5 V −4 −1.5 +2 LSB DNL VDD = 3 V, TA = 25°C −5 −2 +5 LSB Voltage Divider Temperature Coefficient ΔVW/ΔT Code = 80H 25 ppm/°C Full-Scale Error VWFSE Code = FFH −20 −12 0 LSB Zero-Scale Error VWZSE Code = 00H 0 6 10 LSB RESISTOR TERMINALS Voltage Range5 V A, VB, VW 0 VDD V Capacitance6 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = 80H 75 pF Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 120 pF Shutdown Supply Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 50 100 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High VIH V DD = 5 V 2.4 V Input Logic Low VIL V DD = 5 V 0.8 V Input Logic High VIH V DD = 3 V 2.1 V Input Logic Low VIL V DD = 3 V 0.6 V Output Logic High VOH R L = 2.2 kΩ to VDD V DD − 0.1 V Output Logic Low VOL I OL = 1.6 mA, VDD = 5 V 0.4 V Input Current IIL V IN = 0 V or 5 V, VDD = 5 V ±1 μA Input Capacitance6 C IL 5 pF POWER SUPPLIES Power Supply Range VDD range 2.7 5.5 V Supply Current (CMOS) IDD V IH = VDD or VIL = 0 V 0.01 5 μA Supply Current (TTL) 8 I DD V IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA Power Dissipation (CMOS)9 P DISS V IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 μW Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% 0.0035 0.008 %/% PSS ΔVDD = 3 V ± 10% 0.05 0.13 %/%

Rev. E | Page 9 of 32 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_1 K R = 1 kΩ 5,000 kHz Total Harmonic Distortion THDW V A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 % VW Settling Time tS V A = VDD, VB = 0 V, ±1% error band 0.5 μs Resistor Noise Voltage eNWB RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz Crosstalk11 C T V A = VDD, VB = 0 V −65 dB 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 μA for VDD = 3 V and IW = 2.5 mA for VDD = 5 V for 1 kΩ version. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

Rev. E | Page 11 of 32 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V, +8 V VA, VB, VW to GND 0 V, VDD Maximum Current IWB, IWA Pulsed ±20 mA IWB Continuous (RWB ≤ 1 kΩ, A Open)1 ±5 mA IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA IAB Continuous (RAB = 1 kΩ/10 kΩ/ 50 kΩ/100 kΩ)1 ±2.1 mA/±2.1 mA/ ±540 μA/±540 μA Digital Input and Output Voltage to GND

0 V, 7 V

Operating Temperature Range −40°C to +125°C Maximum Junction Temperature (TJ Maximum) 150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Package Power Dissipation (TJ max − TA)/θJA Thermal Resistance (θJA) SOIC (R-8) 158°C/W PDIP (N-14) 83°C/W PDIP (N-24) 63°C/W SOIC (R-14) 120°C/W SOIC (R-24) 70°C/W TSSOP-14 (RU-14) 180°C/W TSSOP-24 (RU-24) 143°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SERIAL DATA-WORD FORMAT Table 6. ADDR DATA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB 29 2 8 2 7 2 0

1 Maximum terminal current is bounded by the maximum applied voltage

across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package; VDD = 5 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrosta tic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge with out detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 9. AD8403 Pin Function Descriptions 4 W2 Wiper RDAC 2, Addr = 012. 8 W4 Wiper RDAC 4, Addr = 112. 10 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4. based on the address bits, and loaded into the target DAC register. 13 SDO Serial Data Output. Open drain transistor requires a pull-up resistor. 14 CLK Serial Clock Input, Positive Edge Triggered. 15 RS Active Low Reset to Midscale. Sets RDAC registers to 80H. 16 V DD Positive Power Supply. Specified for operation at both 3 V and 5 V. 18 W3 Wiper RDAC 3, Addr = 102. 22 W1 Wiper RDAC 1, Addr = 002. 1 All AGND pins must be connected to DGND.

bits, MSB first, followed by eight data bits, also MSB first.

10 MHz makes it possible to load all four VRs under 4 μs

are shown in Figure 3, Figure 4, and Figure 5. preset, so the wiper can be at any random position at power-up. pin, simplifying initial conditions at power-up. Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100. diagram of the equivalent RDAC circuit. latch, and RAB is the nominal end-to-end resistance.

Figure 48. AD8403 Block Diagram Table 12. Input Logic Control Truth Table1 on A1, A0 decode (Table 13).

1 P = positive edge, X = don’t care, SR = shift register

and the pull-up for interface to the next device could be set at 5 V . in the proper decoding location. Table 13. Address Decode Table Figure 49. Equivalent Input Control Logic change all four VR settings. Figure 50. Detailed SDO Output Schematic of the AD8403

6.40 BSC

0.10 COPLANARITY

Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP]

Rev. E | Page 30 of 32 ORDERING GUIDE Model1, 2, 3 Number of Channels End-to-End R AB (kΩ) Temperature Range (°C) Package

Description

Quantity Branding Information AD8400AR10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10 AD8400AR10-REEL 1 10 −40 to +125 8- Lead SOIC_N R-8 2,500 AD8400A10 AD8400ARZ10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10 AD8400ARZ10-REEL 1 10 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A10 AD8400AR50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50 AD8400AR50-REEL 1 50 −40 to +125 8- Lead SOIC_N R-8 2,500 AD8400A50 AD8400ARZ50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50 AD8400ARZ50-REEL 1 50 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A50 AD8400AR100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC AD8400AR100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC AD8400ARZ100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC AD8400ARZ100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC AD8400AR1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1 AD8400AR1-REEL 1 1 −40 to +125 8- Lead SOIC_N R-8 2,500 AD8400A1 AD8400ARZ1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1 AD8400ARZ1-REEL 1 1 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A1 AD8402AN10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10 AD8402ANZ10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10 AD8402AR10 2 10 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A10 AD8402AR10-REEL 2 10 −40 to +125 14- Lead SOIC_N R-14 2,500 AD8402A10 AD8402ARU10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10 AD8402ARU10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10 AD8402ARUZ10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10 AD8402ARUZ10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10 AD8402ARZ10 2 10 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A10 AD8402ARZ10-REEL 2 10 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A10 AD8402AR50 2 50 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A50 AD8402AR50-REEL 2 50 −40 to +125 14- Lead SOIC_N R-14 2,500 AD8402A50 AD8402ARU50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50 AD8402ARU50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50 AD8402ARUZ50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50 AD8402ARUZ50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50 AD8402ARZ50 2 50 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A50 AD8402ARZ50-REEL 2 50 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A50 AD8402AR100 2 100 −40 to +125 14-Lead SOIC_N R-14 56 AD8402AC AD8402AR100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC AD8402ARU100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C AD8402ARU100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C AD8402ARUZ100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C AD8402ARUZ100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C AD8402ARZ100 2 100 −40 to +125 14-Lead SOIC_N R-14 96 AD8402AC AD8402ARZ100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC AD8402AR1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1 AD8402AR1-REEL 2 1 −40 to +125 14- Lead SOIC_N R-14 2,500 AD8402A1 AD8402ARU1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 8402A1 AD8402ARUZ1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 AD8402A1 AD8402ARUZ1-REEL 2 1 −40 to +125 14-Lead TSSOP RU-14 2,500 AD8402A1 AD8402ARZ1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1 AD8402ARZ1-REEL 2 1 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A1

Rev. E | Page 31 of 32 Model1, 2, 3 Number of Channels End-to-End R AB (kΩ) Temperature Range (°C) Package Quantity Branding Information AD8403AN10 4 10 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A10 AD8403AR10 4 10 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A10 AD8403AR10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A10 AD8403ARU10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10 AD8403ARU10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10 AD8403ARUZ10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10 AD8403ARUZ10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10 AD8403ARZ10 4 10 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A10 AD8403ARZ10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A10 AD8403AN50 4 50 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A50 AD8403AR50 4 50 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A50 AD8403AR50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A50 AD8403ARU50 4 50 −40 to +125 24-Lead TSSOP RU-24 63 8403A50 AD8403ARUZ50 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50 AD8403ARUZ50-REEL 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50 AD8403ARZ50 4 50 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A50 AD8403ARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A50 AD8403AR100 4 100 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A100 AD8403AR100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A100 AD8403ARU100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100 AD8403ARU100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100 AD8403ARUZ100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100 AD8403ARUZ100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100 AD8403ARZ100 4 100 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A100 AD8403ARZ100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A100 AD8403AR1 4 1 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A1 AD8403AR1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A1 AD8403ARU1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1 AD8403ARU1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1 AD8403ARUZ1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1 AD8403ARUZ1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1 AD8403ARZ1 4 1 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A1 AD8403ARZ1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A1 AD8403WARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500 EVAL-AD8403SDZ Evaluation Board 1 Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of production and WW is the work week. For example, a non-lead-free part manufactured in the 30th work week of 2005 has the date code of either 530 or 0530, while a lead-free part has the date code of #530. 2 Z = RoHS Compliant Part. 3 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8403W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. E | Page 32 of 32 NOTES © 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D01092-0-7/10(E)