84037012A

SN54HC00 TI | Alldatasheet

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SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E – DECEMBER 1982 – REVISED AUGUST 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Wide Operating Voltage Range of 2 V to 6 V /C0068 Outputs Can Drive Up To 10 LSTTL Loads /C0068 Low Power Consumption, 20-µA Max ICC /C0068 Typical tpd = 8 ns /C0068 ±4-mA Output Drive at 5 V /C0068 Low Input Current of 1 µA Max GND V CC SN54HC00 ...J O R W PACKAGE SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 11 21 3 NC NC NC NC NC V GND NC SN54HC00 . . . FK PACKAGE (TOP VIEW) CC NC – No internal connection description/ordering information The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING –40 C to 85C PDIP – N Tube of 25 SN74HC00N SN74HC00N –40 C to 85C SOIC – D Tube of 50 SN74HC00D HC00 –40 C to 85C SOIC – D Reel of 2500 SN74HC00DR HC00 –40 C to 85C Reel of 250 SN74HC00DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC00NSR HC00 SSOP – DB Reel of 2000 SN74HC00DBR HC00 TSSOP – PW Tube of 90 SN74HC00PW HC00TSSOP – PW Reel of 2000 SN74HC00PWR HC00 Reel of 250 SN74HC00PWT –55 C to 125C CDIP – J Tube of 25 SNJ54HC00J SNJ54HC00J –55°C to 125°C CFP – W Tube of 150 SNJ54HC00W SNJ54HC00W LCCC – FK Tube of 55 SNJ54HC00FK SNJ54HC00FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E – DECEMBER 1982 – REVISED AUGUST 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(each gate) INPUTS OUTPUT A B OUTPUT Y H H L L XH X L H logic diagram (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC00 SN74HC00 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V V High-level input voltage VCC = 2 V 1.5 1.5 VVIH High-level input voltage VCC = 4.5 V 3.15 3.15 VIH VCC = 6 V 4.2 4.2 V Low-level input voltage VCC = 2 V 0.5 0.5 VVIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VIL VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V t/v Input transition rise/fall time VCC = 2 V 1000 1000 ns∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E – DECEMBER 1982 – REVISED AUGUST 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC00 SN74HC00 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT V V = V or V I = –20 A 2 V 1.9 1.998 1.9 1.9 VV V = V or V VVOH VI = VIH or VIL OH 6 V 5.9 5.999 5.9 5.9 VOH II H I L V V = V or V I = 20 A 2 V 0.002 0.1 0.1 0.1 VV V = V or V VVOL VI = VIH or VIL OL 6 V 0.001 0.1 0.1 0.1 VOL II H I L II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA C i 2 V to 6 V 3 10 10 10 pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC00 SN74HC00 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT t A or B Y

2 V 45 90 135 115

nstpd A or B Y 4.5 V 9 18 27 23 nspd

6 V 8 15 23 20

2 V 38 75 110 95

nstt Y 4.5 V 8 15 22 19 nst

6 V 6 13 19 16

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per gate No load 20 pF

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. PLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8403701VCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 5962-8403701VDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC 84037012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8403701CA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 8403701DA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/65001B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/65001BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/65001BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SN54HC00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SN74HC00ADBLE OBSOLETE SSOP DB 14 None Call TI Call TI SN74HC00D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC00DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC00DT ACTIVE SOIC D 14 250 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC00N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74HC00N3 OBSOLETE PDIP N 14 None Call TI Call TI SN74HC00NS ACTIVE SO NS 14 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC00NSLE OBSOLETE SO NS 14 None Call TI Call TI SN74HC00NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC00PW ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC00PWLE OBSOLETE TSSOP PW 14 None Call TI Call TI SN74HC00PWR ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC00PWT ACTIVE TSSOP PW 14 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SNJ54HC00FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54HC00J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SNJ54HC00W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 Addendum-Page 1

Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Mar-2005 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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