HM-6516 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Industry Standard Pinout CC
  • TTL Compatible
  • Static Memory Cells
  • High Output Drive
  • On-Chip Address Latches
  • Easy Microprocessor Interfacing

Description

The HM-6516 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also gives fast access times. The pinout of the HM-6516 is the popular 24 pin, 8-bit wide JEDEC standard, which allows easy memory board layouts, flexible enough to accommo- date a variety of PROMs, RAMS, EPROMs, and ROMs. The HM-6516 is ideally suited for use in microprocessor based systems. The byte wide organization simplifies the memory array design, and keeps operating power down to a minimum, because only one device is enabled at a time. The address latches allow very simple interfacing to recent gen- eration microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable.

Ordering Information

120ns 200ns TEMP. RANGE PACKAGE PKG. NO. HM1-6516B-9 HM1-6516-9 -40 oC to +85oC CERDIP F24.6 - 29102BJA -55 oC to +125oC JAN# F24.6 8403607JA 8403601JA -55 oC to +125oC SMD# F24.6 - HM4-6516-9 -40 oC to +85oC CLCC J32.A 8403607ZA 8403601ZA -55 oC to +125oC SMD# J32.A Pinouts HM-6516 (CERDIP) TOP VIEW HM-6516 (CLCC) TOP VIEW DQ0 DQ1 DQ2 GND VCC W G A10 DQ7 DQ5 DQ4 DQ3 E DQ6 3 2 14 32 31 30 16 17 18 19 2014 15 NC DQ0 DQ1 DQ2 GND NC DQ3 DQ4 DQ5 VCC NC NC NC NC NC NC G A10 E DQ7 DQ6 W PIN DESCRIPTION NC No Connect A0 - A10 Address Inputs E Chip Enable/Power Down VSS /GND Ground DQ0 - DQ7 Data In/Data Out VCC Power (+5V) W Write Enable G Output Enable File Number 2998.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

A A A3 A2 A1 A0 L LG G

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A A GATED COLUMN DECODER LATCHED ADDRESS REGISTER LATCHED ADDRESS REGISTER GATED ROW DECODER 128 x 128 MATRIX A E W G A 16 16 16 1616 16 16 16 DQ0 THRU DQ7 HM-6516

Absolute Maximum Ratings Thermal Information VCC +0.3V Operating Conditions Operating Temperature Ranges: oC to +85oC Thermal Resistance θJA θJC Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX ICCSB Standby Supply Current - 50 µA IO = 0mA, VI = V CC or GND, VCC = 5.5V, HM-6516B-9 - 100 µA IO = 0mA, VI = V CC or GND, HM-6516-9 ICCOP Operating Supply Current (Note 1) - 10 mA f = 1MHz, IO = 0mA, G = VCC , VCC = 5.5V, VI = VCC or GND ICCDR Data Retention Supply Current - 25 µAV CC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC , HM-6516B-9 -5 0 µAV CC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC , HM-6516-9 VCCDR Data Retention Supply Voltage 2.0 - V II Input Leakage Current -1.0 +1.0 µA VI = V CC or GND, VCC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = V CC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V V CC = 4.5V VIH Input High Voltage 2.4 V CC +0.3 V V CC = 5.5V VOL Output Low Voltage - 0.4 V IO = 3.2mA, V CC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -1.0mA, V CC = 4.5V VOH2 Output High Voltage (Note 2) V CC -0.4 - V IO = -100 µA, VCC = 4.5V Capacitance TA = +25oC SYMBOL PARAMETER MAX UNITS TEST CONDITIONS CI Input Capacitance (Note 2) 8 pF f = 1MHz, All measurements are referenced to device GND CIO Input/Output Capacitance (Note 2) 10 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP . 2. Tested at initial design and after major design changes. HM-6516

(1)TELQV Chip Enable Access Time - 120 - 200 ns (Notes 1, 3) (2)TAVQV Address Access Time - 120 - 200 ns (Notes 1, 3, 4) (3)TELQX Chip Enable Output Enable Time 10 - 10 - ns (Notes 2, 3) (4)TWLQZ Write Enable Output Disable Time - 50 - 80 ns (Notes 2, 3) (5)TEHQZ Chip Enable Output Disable Time - 50 - 80 ns (Notes 2, 3) (6)TGLQV Output Enable Output Valid Time - 80 - 80 ns (Notes 1, 3) (7)TGLQX Output Enable Output Enable Time 10 - 10 - ns (Notes 2, 3) (8)TGHQZ Output Enable Output DisableTime - 50 - 80 ns (Notes 2, 3) (9)TELEH Chip Enable Pulse Negative Width 120 - 200 - ns (Notes 1, 3) (10)TEHEL Chip Enable Pulse Positive Width 50 - 80 - ns (Notes 1, 3) (11)TAVEL Address Setup Time 0 - 0 - ns (Notes 1, 3) (12)TELAX Address Hold Time 30 - 50 - ns (Notes 1, 3) (13)TWLWH Write Enable Pulse Width 120 - 200 - ns (Notes 1, 3) (14)TWLEH Write Enable Pulse Setup Time 120 - 200 - ns (Notes 1, 3) (15)TELWH Write Enable Pulse Hold Time 120 - 200 - ns (Notes 1, 3) (16)TDVWH Data Setup Time 50 - 80 - ns (Notes 1, 3) (17)TWHDX Data Hold Time 10 - 10 - ns (Notes 1, 3) (18)TELEL Read or Write Cycle Time 170 - 280 - ns (Notes 1, 3) NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF , access time is derated by 0.15ns per pF . 2. Tested at initial design and after major design changes. 3. V CC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. HM-6516

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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G can be held high (inactive). FIGURE 3. TYPICAL ICCDR vs TA