SN54ALS645A_16 TI1 | Alldatasheet
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SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 – JANUARY 1995 Copyright 1995, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
- Bidirectional Bus Transceivers in High-Density 20-Pin Packages
- True Logic
- 3-State Outputs
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the level at the direction-control (DIR) input. The output-enable (OE ) input can be used to disable the device so that the buses are effectively isolated. The -1 version of the SN74ALS645A is identical to the standard version, except that the recommended maximum I OL is increased to 48 mA. There is no -1 version of the SN54ALS645A. The SN54ALS645A and SN54AS645 are characterized for operation over the full military temperature range of –55°C to 125 °C. The SN74ALS645A and SN74AS645 are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OPERATION OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation DIR GND V CC OE SN54ALS645A, SN54AS645 ...J PACKAGE SN74ALS645A, SN74AS645 . . . DW OR N PACKAGE (TOP VIEW) 3212 0 1 9 9 10 11 12 13 SN54ALS645A, SN54AS645 . . . FK PACKAGE (TOP VIEW)A2 DIR B6 OE GND VCC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 – JANUARY 1995
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol† logic diagram (positive logic) OE
3 EN2 [AB]
3 EN1 [BA]
To Seven Other Transceivers † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS645A SN74ALS645A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –12 –15 mA IOL Low level output current 12 24 mAIOL Low-level output current 48§ mA TA Operating free-air temperature –55 125 0 70 °C § Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V
SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 – JANUARY 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS645A SN74ALS645A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VCC = 4.5 V to 5.5 V,IOH = –0.4 mA VCC –2 VCC –2 VOH IOH = –3 mA 2.4 3.2 2.4 3.2 VVOH VCC = 4.5 V IOH = –12 mA 2 V IOH = –15 mA 2 IOL = 12 mA 0.25 0.4 0.25 0.4 VOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V IOL = 48 mA‡ 0.35 0.5 II Control inputs VCC =55V VI = 7 V 0.1 0.1 mAII A or B ports VCC = 5.5 V VI = 5.5 V 0.1 0.1 mA IIH Control inputs VCC =55V VI=27V 20 20 µAIIH A or B ports§ VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL Control inputs VCC =55V VI=04V –0.1 –0.1 mAIIL A or B ports§ VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA IO ¶ VCC = 5.5 V, VO = 2.25 V –20 –1 12 –30 –1 12 mA Outputs high 30 48 30 45 ICC VCC = 5.5 V Outputs low 36 60 36 55 mA Outputs disabled 38 63 38 58 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V § For I/O ports, the parameters IIH and IIL include the off-state output current. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX# UNIT SN54ALS645A SN74ALS645A MIN MAX MIN MAX tPLH Ao rB Bo rA 1 19 3 10 ns tPHL A or B B or A 1 14 3 10 ns tPZH OE Ao rB 2 30 5 20 ns tPZL OE A or B 2 29 5 20 ns tPHZ OE Ao rB 2 14 2 10 ns tPLZ OE A or B 2 30 4 15 ns # For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 – JANUARY 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS645 SN74AS645 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current 48 64 mA TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS645 SN74AS645 UNITPARAMETER TEST CONDITIONS MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V,IOH = –2 mA VCC –2 VCC –2 VOH IOH = –3 mA 2.4 3.2 2.4 3.2 VVOH VCC = 4.5 V IOH = –12 mA 2.4 V IOH = –15 mA 2.4 VOL VCC =45V IOL = 48 mA 0.3 0.55 VVOL VCC = 4.5 V IOL = 64 mA 0.35 0.55 V II Control inputs VCC =55V VI = 7 V 0.1 0.1 mAII A or B ports VCC = 5.5 V VI = 5.5 V 0.1 0.1 mA IIH Control inputs VCC =55V VI=27V 20 20 µAIIH A or B ports§ VCC = 5.5 V, VI = 2.7 V 70 70 µA IIL Control inputs VCC =55V VI=04V –0.5 –0.5 mAIIL A or B ports§ VCC = 5.5 V, VI = 0.4 V –0.75 –0.75 mA IO ¶ VCC = 5.5 V, VO = 2.25 V –50 –150 –50 –150 mA Outputs high 62 97 62 97 ICC VCC = 5.5 V Outputs low 95 149 95 149 mA Outputs disabled 79 123 79 123 ‡ All typical values are at VCC = 5 V, TA = 25°C. § For I/O ports, the parameters IIH and IIL include the off-state output current. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS .
SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDAS278 – JANUARY 1995 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX† UNIT SN54AS645 SN74AS645 MIN MAX MIN MAX tPLH Ao rB Bo rA 2 11 2 9.5 ns tPHL A or B B or A 2 10.5 2 9 ns tPZH OE Ao rB 2 12 2 11 ns tPZL OE A or B 2 12 2 10 ns tPHZ OE Ao rB 2 8 2 7 ns tPLZ OE A or B 2 13 2 12 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms
www.ti.com 17-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 8403301RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8403301RA SNJ54ALS645AJ 8403301SA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 8403301SA SNJ54ALS645AW SN54ALS645AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54ALS645AJ SN54AS645J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54AS645J SN74ALS645A-1DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A-1 SN74ALS645A-1DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A-1 SN74ALS645A-1DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A-1 SN74ALS645A-1N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS645A-1N SN74ALS645A-1N3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SN74ALS645A-1NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS645A-1N SN74ALS645A-1NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A-1 SN74ALS645ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A SN74ALS645ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A SN74ALS645AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS645AN SN74ALS645AN3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SN74ALS645ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS645A SN74AS645DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS645 SN74AS645DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS645
www.ti.com 17-Dec-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74AS645N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS645N SN74AS645NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS645N SNJ54ALS645AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8403301RA SNJ54ALS645AJ SNJ54ALS645AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 8403301SA SNJ54ALS645AW SNJ54AS645FK OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 SNJ54AS645J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54AS645J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
www.ti.com 17-Dec-2015 Addendum-Page 3 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS645A, SN54AS645, SN74ALS645A, SN74AS645 :
- Catalog: SN74ALS645A , SN74AS645
- Military: SN54ALS645A , SN54AS645 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS645A-1DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS645A-1NSR SO NS 20 2000 367.0 367.0 45.0 SN74ALS645ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS645ANSR SO NS 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP10.63 9.97
2.65 MAX
18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200
www.ti.com EXAMPLE BOARD LAYOUT (9.3)
0.07 MAX
0.07 MIN
20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X
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