84032013A

SNJ54ALS873B TI | Alldatasheet

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Technical content

SN54ALS873B, SN54AS873A . . . JT PACKAGE SN74ALS873B, SN74AS873A . . . DW OR NT PACKAGE (TOP VIEW) SN54ALS873B, SN54AS873A . . . FK PACKAGE (TOP VIEW) 1CLR 1OE 1D1 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OE GND VCC 1LE 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2LE 2CLR NC – No internal connection 1 28 27 12 13 1Q2 1Q3 1Q4 NC 2Q1 2Q2 2Q3 1D2 1D3 1D4 NC 2D1 2D2 2D3 14 15 16 17 18 2D4 2OE GND NC 2CLR 2LE 2Q4 1D1 1OE 1CLR NC 1LE 1Q1 VCC SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 Copyright  1995, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Bus-Structured Pinout
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

description

These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear (CLR) input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable (OE) input is at a high logic level. The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS OUTPUT OE CLR LE D Q L L X X L L H H H H L H H L L L H L X H X X X Z PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic symbol† logic diagram (each quad latch, positive logic) 2OE 1CLR 1OE EN 1LE 1D1 1D2 1D3 1D4 1Q1 1Q2 1Q3 1Q4 C EN 2LE 2D1 2D2 2D3 2D4 2Q1 2Q2 2Q3 2Q4 C 2CLR R R R R OE LE CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC 7 V Input voltage, VI 7 V Voltage applied to a disabled 3-state output 5.5 V Operating free-air temperature range, TA: SN54ALS873B –55°C to 125°C SN74ALS873B 0°C to 70°C Storage temperature range –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS873B SN74ALS873B UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –2.6 mA IOL Low-level output current mA TA Operating free-air temperature –55 125

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS873B SN74ALS873B UNIT PARAMETER TEST CONDITIONS MIN TYP† MAX MIN TYP† MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC– 2 VCC– 2 VOH VCC = 4 5 V IOH = –1 mA 2.4 3.3 V VCC = 4.5 V IOH = –2.6 mA 2.4 3.2 VOL VCC = 4 5 V IOL = 12 mA 0.25 0.4 0.25 0.4 V VOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V µA IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V µA IIL VCC = 5.5 V, VI = 0.4 V – 0.2 – 0.2 mA IO‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA Outputs high ICC VCC = 5.5 V Outputs low mA Outputs disabled † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ALS873B SN74ALS873B UNIT MIN MAX MIN MAX UNIT t Pulse duration CLR low ns tw Pulse duration LE high ns tsu Setup time, data before LE↓ ns th Hold time, data after LE↓ ns

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† UNIT SN54ALS873B SN74ALS873B MIN MAX MIN MAX tPLH D Q ns tPHL D Q ns tPLH LE Q ns tPHL LE Q ns tPHL CLR Q ns tPZH OE Q ns tPZL OE Q ns tPHZ OE Q ns tPLZ OE Q ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC 7 V Input voltage, VI 7 V Voltage applied to a disabled 3-state output 5.5 V Operating free-air temperature range, TA: SN54AS873A –55°C to 125°C SN74AS873A 0°C to 70°C Storage temperature range –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS873A SN74AS873A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current mA TA Operating free-air temperature –55 125

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS873A SN74AS873A UNIT PARAMETER TEST CONDITIONS MIN TYP† MAX MIN TYP† MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC– 2 VCC– 2 VOH VCC = 4 5 V IOH = –12 mA 2.4 3.2 V VCC = 4.5 V IOH = –15 mA 2.4 3.3 VOL VCC = 4 5 V IOL = 32 mA 0.25 0.5 V VOL VCC = 4.5 V IOL = 48 mA 0.35 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V µA IOZL VCC = 5.5 V, VO = 0.4 V –50 –50 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V µA IIL VCC = 5.5 V, VI = 0.4 V – 0.5 – 0.5 mA IO‡ VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA Outputs high 110 110 ICC VCC = 5.5 V Outputs low 109 109 mA Outputs disabled 129 129 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54AS873A SN74AS873A UNIT MIN MAX MIN MAX UNIT t * Pulse duration CLR low ns tw* Pulse duration LE high ns tsu* Setup time, data before LE↓ ns th* Hold time, data after LE↓ 4.5 4.5 ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D – APRIL 1982 – REVISED AUGUST 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† UNIT SN54AS873A SN74AS873A MIN MAX MIN MAX tPLH D Q 12.5 9.5 ns tPHL D Q 8.5 7.5 ns tPLH LE Q 15.5 ns tPHL LE Q 7.5 ns tPHL CLR Q 10.5 ns tPZH OE Q 6.5 ns tPZL OE Q 10.5 ns tPHZ OE Q 7.5 ns tPLZ OE Q 8.5 7.5 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) 84032013A ACTIVE LCCC FK None Call TI Level-NC-NC-NC 8403201KA OBSOLETE CFP W None Call TI Call TI 8403201LA ACTIVE CDIP JT None Call TI Level-NC-NC-NC SN54ALS873BJT ACTIVE CDIP JT None Call TI Level-NC-NC-NC SN74ALS873BDW ACTIVE SOIC DW Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74ALS873BDWR ACTIVE SOIC DW 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74ALS873BNT ACTIVE PDIP NT Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS873BNT3 OBSOLETE PDIP NT None Call TI Call TI SN74AS873ADW OBSOLETE SOIC DW None Call TI Call TI SN74AS873ADWR OBSOLETE SOIC DW None Call TI Call TI SN74AS873ANT OBSOLETE PDIP NT None Call TI Call TI SNJ54ALS873BFK ACTIVE LCCC FK None Call TI Level-NC-NC-NC SNJ54ALS873BJT ACTIVE CDIP JT None Call TI Level-NC-NC-NC SNJ54AS873AFK OBSOLETE LCCC FK None Call TI Call TI SNJ54AS873AJT OBSOLETE CDIP JT None Call TI Call TI SNJ54AS873AW OBSOLETE CFP W None Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

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