8402AKI

ICS8402I IDT | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Two LVCMOS/LVTTL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 15.625MHz to 350MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and output dividers
• RMS period jitter: 30ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• Full 3.3V or mixed 3.3V core/2.5V output supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram HiPerClockS™ ICS OSC OE0 OE1 VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL TEST CONFIGURATION INTERFACE LOGIC ÷ M PHASE DETECTOR ÷16 MR 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XT AL_OUT TEST_CL K XTAL_SEL V DDA S_LOAD S_DATA S_CLOCK MR nc GND XTAL_IN nP_LOAD VCO_SEL M4TEST VDD VDDO OE1 OE0 GND Pin Assignment ICS8402I

32 Lead LQFP

7mm x 7mm x 1.4mm package body Y Package Top View

32 Lead VFQFN

5mm x 5mm x 0.925mm package body K Package Top View

Characteristics, Table 5, NOTE 1. fundamental crystal is used as the input to the on-chip oscillator. output of the M divider is also applied to the phase detector.

00 L O W

*NOTE: The NULL timing slot must be observed. Figure 1. Parallel & Serial Load Operations

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

1 M5 Input Pullup

M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. 5, 6 N0, N1 Input Pulldown Determines output divider value as defined in Table 3C, Function Table. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. 10 V DD Power Core supply pin. Output enable. When logic HIGH, the outputs are enabled (default). OE Function Table. LVCMOS / LVTTL interface levels. 13 V DDO Power Output supply pin. 14, 15 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.

17 MR Input Pulldown

values. LVCMOS/LVTTL interface levels.

18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on the

rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 19 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. 21 V DDA Power Analog supply pin.

22 XTAL_SEL Input Pullup

Selects between crystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS/LVTTL interface levels. XTAL_IN Input Crystal oscillator interf ace. XTAL_IN is the input, XTAL_OUT is the output. divider, and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL interface levels.

Table 2. Pin Characteristics H X X X X X X Reset. Forces outputs LOW. and N output divider. TEST output forced LOW. until next LOW transition or until a serial event occurs. S_DATA on each rising edge of S_CLOCK. M divider and N output divider. LHX X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LHX XH ↑ Data S_DATA passed directly to M divider as it is clocked.

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 5 ICS8402AYI REV. A OCTOBER 16, 2007 Table 3B. Programmable VCO Frequency Function Table NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 25MHz. Table 3C. Programmable Output DividerFunction Table Table 3D. OE Function Table VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 2 5 0 1 0 000001010 2 7 5 1 1 000001011 6 5 0 2 6 000011010 6 7 5 2 7 000011011 7 0 0 2 8 000011100 Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 2 125 350 0 1 4 62.5 175 1 0 8 31.25 87.5 1 1 16 15.625 43.75 Inputs Output OE0 OE1 Q0 Q1 0 0 Hi-Z Hi-Z 0 1 Hi-Z Enabled 1 0 Enabled Hi-Z 1 1 Enabled Enabled

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 6 ICS8402AYI REV. A OCTOBER 16, 2007 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 125 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 10 mA

NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 5. Input Frequency Characteristics, TA = -40°C to 85°C 40MHz, valid values of M are 7 ≤ M ≤ 17.

Table 6. Crystal Characteristics See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 9 ICS8402AYI REV. A OCTOBER 16, 2007 Table 7B. AC Characteristics, VDD = 3.3V±5%,VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 15.625 350 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3 40 100 ps tjit(per) Period Jitter, RMS; NOTE 1 30 ps tsk(o) Output Skew; NOTE 2, 3 60 ps tR / tF Output Rise/Fall Time 20% to 80% 0.25 1.0 ns tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle ƒ ≤ 300MHz 40 60 % t LOCK PLL Lock Time 1m s

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 10 ICS8402AYI REV. A OCTOBER 16, 2007 Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit Output Skew Cycle-to-Cycle Jitter 3.3V/2.5V LVPECL Output Load AC Test Circuit Period Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx LVCMOS GND VDD, 1.65V±5% -1.65V±5% VDDA, VDDO tsk(o) Qx Qy ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

Q0, Q1 SCOPE Qx LVCMOS VDDO GND 2.05V±5% -1.25V±5% VCC, VCCO 1.25V±5% VCCA VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0, Q1

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 11 ICS8402AYI REV. A OCTOBER 16, 2007 Parameter Measurement Information, continued Output Rise/Fall Time

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8402I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each V DDA pin. Figure 2. Power Supply Filtering

resistor can be tied from the TEST_CLK to ground. protection. A 1kΩ resistor can be used. recommend that there is no trace attached. the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadfame Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 14 ICS8402AYI REV. A OCTOBER 16, 2007 Reliability Information Table 8A. θJA vs. Air Flow Table for a 32 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 8B. θJA vs. Air Flow Table for a 32 Lead VFQFN Transistor Count The transistor count for ICS8402I is: 3784 θJA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W θJA vs. Air Flow Linear Feet per Minute 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 37°C/W 32.4°C/W 29.0°C/W

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 15 ICS8402AYI REV. A OCTOBER 16, 2007 Package Outline and Package Dimension Package Outline - Y Suffix for 32 Lead LQFP Table 9A. Package Dimensions for 32 Lead LQFP Reference Document: JEDEC Publication 95, MS-026 JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 16 ICS8402AYI REV. A OCTOBER 16, 2007 Package Outline - K Suffix for 32 Lead VFQFN NOTE:The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. Table 9B. Package Dimensions for 32 Lead VFQFN Reference Document: JEDEC Publication 95, MO-220 JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 00 . 0 5 A3 0.25 Ref. b 0.18 0.25 0.30 ND & NE 8 D & E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 17 ICS8402AYI REV. A OCTOBER 16, 2007

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER 18 ICS8402AYI REV. A OCTOBER 16, 2007 Revision History Sheet Rev Table Page Description of Change Date A T9B T10 Pin Assignment - added 32 Lead VFQFN information. Absolute Maximum Ratings - added 32 Lead VFQFN package thermal impedance. Added LVCMOS to XTAL Interface section. Added Recommendations for Unused Input/Output Pins section. Added VFQFN EPAD Thermal Release Path section. Added 32 Lead VFQFN Reliability Information. Added 32 Lead VFQFN Package Dimensions Table and Package Outline Ordering Information Table - added 32 Lead VFQFN ordering information. 10/10/07

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