ICS840272I IDT | Alldatasheet

Document overview

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Technical content

Features

  • Two single-ended outputs (LVCMOS or LVTTL levels), output impedance: 17Ω
  • Single-ended lock detect output (LVCMOS or LVTTL levels)
  • Two selectable differential clock inputs
  • Differential input pair (CLKx, nCLKx) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels
  • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
  • Selectable input frequencies: 161.1328MHz, 156.25MHz or 125MHz
  • Output frequency: 25MHz, 8kHz
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package1 9GND VDDA OE SEL1 SEL0 REF_SEL LOCK_DT VDD VDDO QA QB GND CLK0 nCLK0 CLK1 nCLK1 Input Control 00 = PLL Bypass, 25MHz Input 01 = 161.1328125MHz (default) 10 = 156.25MHz 11 = 125MHz M QA LOCK_DT 25MHz 8kHz QB CLK0 nCLK0 Pullup/Pulldown Pulldown CLK1 nCLK1 REF_SEL P N PLL ÷3125 Pullup/Pulldown Pulldown Pulldown SEL[1:0] Pulldown:Pullup OE Pulldown ICS840272I

16 Lead TSSOP

4.40mm x 5.0mm x 0.925mm package body G Package Top View Pin Assignment Block Diagram

ICS840272AGI REVISION A JULY 26, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DD Power Core supply pin. 2 LOCK_DT Output Lock detect. Logic HIGH when PLL is locked. 3 REF_SEL Input Pulldown Selects the input reference clock. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1, nCLK1. LVCMOS/LVTTL interface levels. 4 SEL0 Input Pullup Selects the input reference frequency and the PLL bypass mode. See Table 3A. LVCMOS/LVTTL interface levels. 5 SEL1 Input Pulldown Selects the input reference frequency and the PLL bypass mode. See Table 3A. LVCMOS/LVTTL interface levels. 6 OE Input Pulldown 8kHz output enable pin. When LOW, QB is disabled. When HIGH, QB is enabled. LVCMOS/LVTTL interface levels. See Table 3B. 7V DDA Power Analog supply pin. 8, 13 GND Power Power supply ground. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 10 CLK1 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 12 CLK0 Input Pulldown Non-inverting differential clock input. 14 QB Output Single-ended clock output. LV CMOS/LVTTL interface levels. 15 QA Output Single-ended clock output. LV CMOS/LVTTL interface levels. 16 V DDO Power Output supply pin.

ICS840272AGI REVISION A JULY 26, 2010 3 ©2010 Integrated Device Technology, Inc. ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Function Tables Table 3A. SEL[1:0] Function Table Table 3B. OE Function Table Inputs Function Output (MHz) SEL1 SEL0 CLKx, nCLKx (MHz) Mode QA 0 0 25 PLL Bypass 25 0 (default) 1 (default) 161.1328125 PLL Enabled 25 1 0 156.25 PLL Enabled 25 1 1 125 PLL Enabled 25 Control Input Function OE QB Output 0 (default) Disabled (High impedance) 1E n a b l e d

ICS840272AGI REVISION A JULY 26, 2010 4 ©2010 Integrated Device Technology, Inc. ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 81.2°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.11 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 57 mA IDDA Analog Supply Current 11 mA IDDO Output Supply Current 5m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage V DD = 3.465V 2 V DD + 0.3 V VIL Input Low Voltage V DD = 3.465V -0.3 0.8 V IIH Input High Current OE, SEL1, REF_SEL VDD = VIN = 3.465V 150 µA SEL0 V DD = VIN = 3.465V 5 µA IIL Input Low Current OE, SEL1, REF_SEL V DD = 3.465V, VIN = 0V -5 µA SEL0 V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage I OH = -12mA 2.6 V VOL Output Low Voltage I OL = 12mA 0.5 V

ICS840272AGI REVISION A JULY 26, 2010 5 ©2010 Integrated Device Technology, Inc. NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 5. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: Refer to Phase Noise plot.

ICS840272AGI REVISION A JULY 26, 2010 6 ©2010 Integrated Device Technology, Inc. ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Typical Phase Noise at 25MHz Noise Power dBc Hz Offset Frequency (Hz) Additive Phase Jitter @ 25MHz 12kHz to 10MHz = 1.1ps (typical)

ICS840272AGI REVISION A JULY 26, 2010 7 ©2010 Integrated Device Technology, Inc. ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR Parameter Measurement Information LVCMOS Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period RMS Phase Jitter Differential Input Level Output Rise/Fall Time Cycle-to-Cycle Jitter SCOPE QxLVCMOS GND VDD, 1.65V±5% -1.65V±5% VDDO VDDA 1.65V±5% tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA, QB Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power nCLK[0:1] CLK[0:1] VDD GND V CMR Cross Points VPP 20% 80% 80% 20% tR tF QA, QB ➤➤ ➤➤ VDDORx VDDORx VDDORx tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA, QB

ICS840272AGI REVISION A JULY 26, 2010 8 ©2010 Integrated Device Technology, Inc. capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering resistance is not required but can be added for additional protection. additional protection, a 1kΩ resistor can be tied from CLK to ground.

ICS840272AGI REVISION A JULY 26, 2010 12 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS840272I. Equations and example calculations are also provided. The total power dissipation for the ICS840272I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection

ICS840272AGI REVISION A JULY 26, 2010 13 ©2010 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 16 Lead TSSOP

ICS840272AGI REVISION A JULY 26, 2010 14 ©2010 Integrated Device Technology, Inc. ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS840272I Data Sheet SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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