840271BGILF

ICS840271I IDT | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

• Clock frequency translator for Synchronous Ethernet

applications

• One single-ended output (LVCMOS or LVTTL levels), 16Ω output impedance
• Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels
• Supports input clock frequencies of: 125MHz, 156.25MHz or 161.1328MHz
• Generates a 25MHz output clock signal
• Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/LVTTL) input levels
• Internal PLL is optimized for low cycle-to-cycle jitter at the output
• Full 3.3V or 2.5V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package HiPerClockS™ ICS ICS840271I

8 Lead TSSOP

4.40mm x 3.0mm x 0.925mm package body G Package Top View Pin Assignment VDDA nCLK CLK SEL0 GND Q SEL1 VDD

25 MHz

Q SEL(1:0) Input Control Logic CLK nCLK 00 = PLL Bypass 01 = 161.1328125 MHz 10 = 156.2500000 MHz 11 = 125.0000000 MHz PLLPre- divider Output divider Feedback divider Block Diagram

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. SEL[1:0] Function Table 1V DDA Power Analog supply pin. 2 SEL0 Input Pulldown Selects the input reference frequency and the PLL bypass mode. LVCMOS/LVTTL interface levels. See Table 3. 3 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 5 SEL1 Input Pullup Selects the input reference frequency and the PLL bypass mode. LVCMOS/LVTTL interface levels. See Table 3. 6 GND Power Power supply ground. 7 Q Output Single-ended clock output. LV CMOS/LVTTL interface levels. 8V DD Power Core supply pin.

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 3 ICS840271BGI REV. A APRIL 23, 2009 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DD + 0.5V Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.08 3.3 V DD V IDD Power Supply Current 75 mA IDDA Analog Supply Current 8m A Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.08 2.5 V DD V IDD Power Supply Current 72 mA IDDA Analog Supply Current 8m A

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 4 ICS840271BGI REV. A APRIL 23, 2009 Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 4D. Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current SEL1 V DD = VIN = 3.465V or 2.625V 5 µA SEL0 V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current SEL1 V DD = 3.465V, VIN = 0V -150 µA SEL0 V DD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage VDD = 3.465V, IOH = 12mA 2.6 V VDD = 2.625V, IOH = 12mA 1.8 V VOL Output Low Voltage V DD = 3.465V or 2.625V, IOL = -12mA 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK/nCLK V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK VDD = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 5 ICS840271BGI REV. A APRIL 23, 2009 Table 5A. AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Table 5B. AC Characteristics, VDD = 2.5V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 25 MHz tjit(cc)) Cycle-to-Cycle Jitter SEL0 ≠ SEL1 40 ps SEL0 = SEL1 = 1 15 ps tLOCK PLL Lock Time SEL1 = 0, SEL0 = 1 1 s SEL 1 = 1, SEL0 = X 50 ms tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 25 MHz tjit(cc)) Cycle-to-Cycle Jitter SEL0 ≠ SEL1 50 ps SEL0 = SEL1 = 1 15 ps tLOCK PLL Lock Time SEL1 = 0, SEL0 = 1 1 s SEL 1 = 1, SEL0 = X 50 ms tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 %

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 6 ICS840271BGI REV. A APRIL 23, 2009 Parameter Measurement Information 3.3V Output Load AC Test Circuit Differential Input Level Output Duty Cycle/Pulse Width/Period 2.5V Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time SCOPE QxLVCMOS GND -1.65V±5% 1.65V±5% VDD VDDA 1.65V±5% nCLK CLK VDD GND V CMR Cross Points V PP tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q SCOPE QxLVCMOS GND -1.25V±5% 1.25V±5% VDD VDDA 1.25V±5% ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q 20% 80% 80% 20% tR tF Q

This section provides information on power dissipation and junction temperature for the ICS840271I. Equations and example calculations are also provided. The total power dissipation for the ICS840271I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR IDT™ / ICS™ SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR 12 ICS840271BGI REV. A APRIL 23, 2009

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR www.IDT.com © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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