84021 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 20
Technical content
Features
- Two LVCMOS/LVTTL outputs
- Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK
- Output frequency range: 103.3MHz to 260MHz
- Crystal input frequency range: 14MHz to 40MHz
- VCO range: 620MHz to 780MHz
- Parallel or serial interface for programming counter and output dividers
- RMS period jitter: 14.7ps (typical), (N ÷ 4, VDDO = 3.3V±5%)
- RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.61ps (typical) Offset Noise Power
- Full 3.3V or mixed 3.3V core/2.5V or 1.8V output supply voltage
- 0°C to 70°C ambient operating temperature
- Industrial temperature information available upon request
- Available in lead-free (RoHS 6) package 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nc GND XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR TEST VDD OE1 OE0 VDDO GND VCO_SEL nP_LOAD XTAL_IN 84021
32 Lead LQFP
7mm x 7mm x 1.4mm package body Y Package Top View Block Diagram Pin Assignment Phase Detector VCO PLL N Configuration Interface Logic OSC VCO_SEL OE1 XTAL_SEL XTAL_IN MR S_LOAD S_DATA S_CLOCK nP_LOAD M[0:8] N[0:1] XTAL_OUT TEST_CLK TEST Pullup Pullup Pullup M5 Pullup; M[0:4, 6:8] Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown OE0
84021 Data Sheet 260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Characteristics, Table 5, NOTE 1. divider is also applied to the phase detector. buffers. The divider provides a 50% output duty cycle. each mode. In parallel mode, the nP_LOAD input is initially LOW. the M divider and N output divider on each rising edge of S_CLOCK. Figure 1. Parallel & Serial Load Operations
00 L O W
*NOTE: The NULL timing slot must be observed.
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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
1 M5 Input Pullup
input. LVCMOS/LVTTL interface levels. Table. LVCMOS/LVTTL interface levels. 8, 16 GND Power Power supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Output enable. When logic HIGH, the outputs are enabled (default). Function Table. LVCMOS/LVTTL interface levels. DDO Power Output supply pin. 14, 15 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17 MR Input Pulldown
loaded M, N, and T values. LVCMOS/LVTTL interface levels.
18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 19 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin.
22 XTAL_SEL Input Pullup
Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels. 23 TEST_CLK Input Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels. value. LVCMOS/LVTTL interface levels. 27 VCO_SEL Input Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL interface levels.
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Table 2. Pin Characteristics H X X X X X X Reset. Forces outputs LOW. N output divider. TEST output forced LOW. next LOW transition or until a serial event occurs. S_DATA on each rising edge of S_CLOCK. LHX X L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. LHX XH Data S_DATA passed directly to M divider as it is clocked.
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Table 3B. Programmable VCO Frequency Function Table(NOTE 1) NOTE 1: These M divide values and the resulting frequencies correspond to TEST_CLK or crystal frequency of 25MHz. Table 3C. Programmable Output Divider Function Table (PLL Enabled) Table 3D. Commonly Used Configuration Function Table Table 3E. Output Enable & Clock Enable Function Table VCO Frequency (MHz) M Divide 2 5 6 1 2 8 6 4 3 2 1 6 8421 M8 M7 M6 M5 M4 M3 M2 M1 M0 6 2 5 2 5 000011001 7 0 0 2 8 000011100 7 7 5 3 1 000011111 Inputs N Divider Value Output Frequency (MHz) N1 N0 Minimum Maximum 0 0 3 206.7 260 0 1 4 155 195 1 0 5 124 156 1 1 6 103.3 130 Inputs Output Frequency (MHz) Crystal (MHz) M Divider Valu e N Divider Value Minimum 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 Control Inputs Output OE0 OE1 Q0 Q1 0 0 Hi-Z Hi-Z 0 1 Hi-Z Enabled 1 0 Enabled Hi-Z 1 1 Enabled Enabled
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.36 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 110 mA IDDA Analog Supply Current 24 mA IDDO Output Supply Current 5m A
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NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams. values of M are 16 M 19. Table 6. Crystal Characteristics
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Table 7A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 103.3 260 MHz tjit(per) Period Jitter, RMS; NOTE 1, 2 N = 3 13.5 26.4 ps N = 4 14.7 34.2 ps N = 5 16.7 42.4 ps N = 6 24.7 40.8 ps M=40, N=4, 16.667MHz XTAL, fOUT=166.67MHz 4.5 6.9 ps M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 4.6 7.8 ps tsk(o) Output Skew; NOTE 2, 3 100 ps tR / tF Output Rise/Fall Time 20% to 80% 100 800 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N 34 4 5 6 % M=40, N=4, 16.667MHz XTAL, f OUT=166.67MHz 45 55 % M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 47 53 % tLOCK PLL Lock Time 1m s
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Table 7B. AC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 103.3 260 MHz tjit(per) Period Jitter, RMS; NOTE 1, 2 N = 3 11.4 18.8 ps N = 4 13.3 28.3 ps N = 5 16.0 39.8 ps N = 6 19.2 32.4 ps M=40, N=4, 16.667MHz XTAL, fOUT=166.67MHz 4.3 6.2 ps M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 4.5 7.7 ps tsk(o) Output Skew; NOTE 2, 3 90 ps tR / tF Output Rise/Fall Time 20% to 80% 100 800 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N 34 4 5 6 % M=40, N=4, 16.667MHz XTAL, f OUT=166.67MHz 45 55 % M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 47 53 % tLOCK PLL Lock Time 1m s
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Table 7C. AC Characteristics, VDD = 3.3V±5%, VDDO = 1.8V±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 103.3 260 MHz tjit(per) Period Jitter, RMS; NOTE 1, 2 N = 3 9.4 13.2 ps N = 4 10.8 19.6 ps N = 5 12.7 32.5 ps N = 6 13.4 25.4 ps M=40, N=4, 16.667MHz XTAL, fOUT=166.67MHz 5.4 8.3 ps M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 5.1 8.8 ps tsk(o) Output Skew; NOTE 2, 3 90 ps tR / tF Output Rise/Fall Time 20% to 80% 100 800 ps tS Setup Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns t H Hold Time M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N 34 0 6 0 % M=40, N=4, 16.667MHz XTAL, f OUT=166.67MHz 44 56 % M=40, N=5, 16.667MHz XTAL, fOUT=133.33MHz 48 52 % tLOCK PLL Lock Time 1m s
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Parameter Measurement Information 3.3V Core/3.3V Output Load AC Test Circuit 3.3V Core/1.8V Output Load AC Test Circuit Output Skew 3.3V Core/2.5V Output Load AC Test Circuit Period Jitter Output Rise/Fall Time SCOPE Qx GND 15ΩVDD, 1.65V±5% -1.65V±5% VDDA VDDO 1.65V±5% SCOPE Qx GND 15Ω VDD VDDA VDDO 2.4V±5% -0.9V±5% 0.9V±5% 2.4V±5% tsk(o) VDDO VDDO Qx Qy SCOPE Qx GND 15Ω VDD VDDA VDDO 2.05V±5% -1.25V±5% 1.25V±5% 2.05V±5% VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10 -7)% of all measurements Histogram 20% 80% 80% 20% tR tF Q[0:1]
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Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: TEST Output The unused TEST output can be left floating. There should be no trace attached. LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:1]
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Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface VCC XTAL_OUT XTAL_IN 100 100 Zo = 50 ohmsRsRo Zo = Ro + Rs .1uf LVCMOS Driver XTAL_OU T XTAL_I N Zo = 50 ohms C2 .1uf LVPECL Driver Zo = 50 ohms 50R3
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approaches are shown in the LVCMOS Termination Application Note. 22pF and C2 = 22pF are approximate values for frequency accuracy. supplies to isolate from coupling into the internal PLL. filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. suggests adding bulk capacitances in the local area of all devices. Figure 3. 84021 Application Schematic Example
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Table 8. JA vs. Air Flow Table for a 32 Lead LQFP
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Table 9. Package Dimensions for 32 Lead LQFP
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Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
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Rev Table Page Description of Change Date B T2 4 Pin Characteristics Table - added ROUT rows. Added Schematic Layout. Changed XTAL naming convention to XTAL_IN/XTAL_OUT throughout the data sheet. 1/5/04 C T6 T10 Features Section - added Lead-Free bullet. Updated Parallel & Serial Load Operations Diagram. Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free package. 6/9/05 D T4A T7A - T7C T10 8 - 10 Features section - updated RMS period jitter spec in bullet; added RMS phase jitter bullet. Block Diagram - added pullups/pulldowns to input pins and added “N” in output divider box. Absolute Maximum Ratings - updated Inputs, V Power Supply DC Characteristics - updated VDDA, IDD, IDDA and IDDO specs. Crystal Characteristics - deleted Drive Level row. Updated Period Jitter, Output Rise/Fall Time and Output Duty Cycle specs. Added thermal note. Parameter Measurement Information - corrected Output Load AC Test Circuit diagrams to coincide with 15 V DDA. Added Recommendations for Unused Input & Output Pins. Deleted Power Supply Filtering Techniques section, added to schematic layout. Added Overdriving the XTAL Interface section. Updated Layout Guideline and diagram. Ordering Information Table - updated Part/Order Numbers and Marking to revision “B”. Converted datasheet format. 1/5/11 E T7A 8 AC Characteristics Table - corrected Period Jitter N = 4 spec, from 32.2ps max. to 34.2ps max. Deleted Crystal Input Interface section, added to the schematic. 8/18/11
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