ICS8402015I IDT | Alldatasheet

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Technical content

Features

  • Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz
  • Crystal input frequency: 25MHz
  • Maximum output frequency: 125MHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (637kHz - 62.5MHz): 0.373ps (typical) LVDS output
  • RMS phase jitter @ 25MHz, using a 25MHz crystal (12kHz - 1MHz): 0.64ps (typical) LVCMOS output
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package HiPerClockS™ ICS 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VDDO_REF REF_OUT GND GND QA0 QA1 QA2 VDDO_A VDDO_C nQC2 QC2 nC1 QC1 nQC0 QC0 VDDO_C VDDO_B QB0 QB1 QB2 GND MR VDD GND XTAL_OUT XTAL_IN OE2 OE1 OE0 VDDA GND GND Pin Assignment ICS8402015I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 2 ©2009 Integrated Device Technology, Inc. Block Diagram OSC Phase Detector VCO 500MHz ÷20 QA0 QA1 QA2 QB0 QB1 QB2 QC0 nQC0 nQC1 QC1 nQC2 QC2 REF_OUT OE1 = Pullup OE0, OE2 = Pulldown 25MHz XTAL_IN XTAL_OUT OE[2:0] OE[2:0] PulldownMR ÷10 ÷20 LVCMOS - 25MHz or 50MHz LVCMOS - 125MHz LVCMOS - 25MHz LVDS - 125MHz OE LOGIC

ICS8402015AKI REVISION A JUNE 25, 2009 3 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDO_REF Power Output supply pin for REF_OUT output. 2 REF_OUT Output Reference clock output. LVCMOS/LVTTL interface levels. 25, 32 GND Power Power supply ground. 5, 6, 7 QA0, QA1, QA2 Output Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels. 8V DDO_A Power Power output supply pin for Bank A LVCMOS outputs. 9V DDO_B Power Power output supply pin for Bank B LVCMOS outputs. 10, 11, 12 QB0, QB1, QB2 Output Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels.

14 MR Input Pulldown

pulled HIGH). LVCMOS/LVTTL interface levels. 15 V DD Power Core supply pin. 17, 24 V DDO_C Power Power output supply pin for Bank C LVDS outputs. 18, 19 QC0, nQC0 Output Differential Bank C clock outputs. LVDS interface levels. 20, 21 QC1, nQC1 Output Differential Bank C clock outputs. LVDS interface levels. 22, 23 QC2, nQC2 Output Differential Bank C clock outputs. LVDS interface levels. 26 V DDA Power Analog supply pin. 27, 29 OE0, OE2 Input Pulldown Output enable and configuration pins. See Table 3. LVCMOS/LVTTL interface levels. 28 OE1 Input Pullup Output enable and configuration pin. See Table 3. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_O UT is the output, XTAL_IN is the input.

ICS8402015AKI REVISION A JUNE 25, 2009 4 ©2009 Integrated Device Technology, Inc. Table 3. OE Function and ConfigurationTable

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 5 ©2009 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DDO_LVCMOS + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Operating Temperature Range, T A -40°C to +85°C Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.36 3.3 V DD V VDDO_A, VDDO_B, VDDO_C, VDDO_REF Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 30 mA IDDA Analog Supply Current 36 mA IDDO_A, IDDO_B, IDDO_C, IDDO_REF Total Output Supply Current Outputs Unused 26 mA

ICS8402015AKI REVISION A JUNE 25, 2009 6 ©2009 Integrated Device Technology, Inc. Table 5. Crystal Characteristics

ICS8402015AKI REVISION A JUNE 25, 2009 7 ©2009 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V±5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 8 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit RMS Phase Jitter Single-Ended Output Duty Cycle/Pulse Width/Period 3.3V LVCMOS Output Load AC Test Circuit Bank Skew Differential Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDD, VDDA VDDO_C Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power QA[0:2], QB[0:2] tPERIOD tPW tPERIOD odc = VDDO_CMOS x 100% tPW SCOPE QxLVCMOS GND VDDA VDDO_A, VDDO_B VDD, 1.65V±5% -1.65V±5% 1.65V±5% Qx[0:2] tsk(b) Qx[0:2] nQC[0:2] Where X = Bank A, Bank B or Bank C outputs nQC[0:2] QC{0:2] nQC{0:2] tPW tPERIOD tPW tPERIOD odc = x 100%

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 9 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information, continued LVCMOS Output Rise/Fall Time High Impedance Leakage Current Setup Differential Output Voltage Setup LVDS Output Rise/Fall Time Differential Output Short Circuit Setup Offset Voltage Setup 20% 80% 80% 20% tR tF QA[0:2], QB[0:2] out out LVDSDC Input 3.3V±5% POWER SUPPL Y Float GND + _ IOZ IOZ 100 out out LVDSDC Input VOD/∆ VOD VDD 20% 80% 80% 20% tR tF VOD QC{0:2] nQC{0:2] out out LVDSDC Input IOSD VDD out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 10 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Short Circuit Current Setup Power Off Leakage Setup

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8402015I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, VDDO_A, VDDO_B, VDDO_C, and VDDO_REF should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering resistance is not required but can be added for additional protection. between the differential pair.

ICS8402015AKI REVISION A JUNE 25, 2009 12 ©2009 Integrated Device Technology, Inc. recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

ICS8402015AKI REVISION A JUNE 25, 2009 13 ©2009 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS8402015AKI REVISION A JUNE 25, 2009 15 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8402015I. Equations and example calculations are also provided. The total power dissipation for the ICS8402015I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

ICS8402015AKI REVISION A JUNE 25, 2009 16 ©2009 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN Table 9. Package Dimensions package dimensions are in Table 9.

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 17 ©2009 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8402015AKI REVISION A JUNE 25, 2009 18 ©2009 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date

ICS8402015I Datasheet FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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