ICS8402010I IDT | Alldatasheet

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FEMTOCLOCK™ CRYSTAL-TO- LVDS/LVCMOS CLOCK GENERATOR ICS8402010I IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 1 ICS8402010AKI REV. A AUGUST 28, 2008 GENERAL DESCRIPTION ICS8402010I is a low phase noise Clock Generator and is a member of the HiperClockS™ family of high performance clock solutions from IDT. The device provides three banks of outputs and a reference clock. Each bank can be independently enabled by using output enable pins. A 25MHz, 18pF parallel resonant crystal is used to generate the 16.66MHz, 62.5MHz and 25MHz frequencies. The typical RMS phase jitter for this device is less than 1ps.

FEATURES

  • Three banks of outputs: Bank A/B: three single-ended LVCMOS outputs at 16.66MHz Bank C: three differential LVDS outputs at 62.5MHz One single-ended reference clock output at 25MHz
  • Crystal input frequency: 25MHz
  • Maximum output frequency: 62.5MHz
  • RMS phase jitter @ 62.5MHz, using a 25MHz crystal, Integration Range (1.875MHz - 20MHz): 0.375ps (typical)
  • Full 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS6) packages HiPerClockS™ ICS PIN ASSIGNMENT BLOCK DIAGRAM OSC Phase Detector VCO 500MHz ÷20 ÷30 QA0 QA1 QA2 QB0 QB1 QB2 QC0 nQC0 nQC1 QC1 nQC2 QC2 REF_OUT Pullup 25MHz XTAL_IN XTAL_OUT OE[2:0] ÷30 LVCMOS - 16.66MHz LVCMOS - 16.66MHz LVCMOS - 25MHz LVDS 62.5MHz ICS8402010I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 VDDO_C nQC2 QC2 nQC1 QC1 nQC0 QC0 VDDO_C VDDO_REF REF_OUT GND GND QA0 QA1 QA2 VDDO_A VDDO_B QB0 QB1 QB2 GND MR V DD GND GND XTAL_OUT XTAL_IN OE2 OE1 OE0 V DDA GND

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OE FUNCTION TABLE

IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 3 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DDO_A, _B + 0.5V Outputs, IO (LVDS, VDDO_C) Continuous Current 10mA Surge Current 15mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 37.0°C/W (0 mps) Junction-to-Ambient Package Thermal Impedance, θJB 0.5°C/W Junction-to-Board Package Thermal Impedance, θJC 29.6°C/W Junction-to-Case NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V ± 5%,T A = -40°C TO 85°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V ± 5%,T A = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC5 31.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 51.0–3 .3V DD V V ,A_ODD V ,B_ODD V ,C_ODD V FER_ODD egatloVylppuStuptuO5 31.3V 3.35 64.3V I DD tnerruCylppuSrewoP 52A m I ADD tnerruCylppuSgolanA 51A m I A_ODD I+ B_ODD + I C_ODD I+ FER_ODD tnerruCylppuStuptuO 03A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V DD 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tupnI tnerruChgiH 2EO,1EO,0EOV DD V= NI V564.3=5 A µ RMV DD V= NI V564.3=0 51A µ I LI tupnI tnerruCwoL 2EO,1EO,0EOV DD V,V564.3= NI V0=0 51-A µ RMV DD V,V564.3= NI V0=5 -A µ V HO tuptuO 1ETON;egatloVhgiH ,TUO_FER ]2:0[BQ,]2:0[AQ V X_ODD 564.3=V 6.2V V LO tuptuO 1ETON;egatloVwoL ,TUO_FER ]2:0[BQ,]2:0[AQ V X_ODD 564.3=V 5.0V V:ETON X_ODD Vsetoned ,A_ODD V B_ODD Vdna .FER_ODD 05htiwdetanimretstuptuO:1ETON Ω Vot FER_,B_,A_ODD ,noitamrofnItnemerusaeMretemaraPeeS.2/ .margaidtiucriCtseTdaoLtuptuO

TABLE 5. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V ± 5%,T A = -40°C TO 85°C TABLE 4. CRYSTAL CHARACTERISTICS

IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 5 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR TYPICAL PHASE NOISE AT 62.5MHZ (LVDS) 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.375ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding Ethernet Filter to raw data

IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 6 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT LVCMOS BANK SKEW LVCMOS OUTPUT SKEW PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS SCOPE Qx LVCMOS GND 1.65V±5% -1.65V±5% VDD, VDDO_A, VDDO_B, VDDO_REF 1.65V±5% t sk(o) VDDO VDDO Qx Qy VDDAVDD, VDDO_C VDDA LVDS BANK SKEW t sk(b) nQCx QCx nQCy QCy t sk(b) VDDO VDDO QXx QXy Where X = A or B Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power

IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 7 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR OFFSET VOL TAGE SETUP LVDS OUTPUT RISE/FALL TIME DIFFERENTIAL OUTPUT VOLTAGE SETUP 100 out out LVDSDC Input VOD/Δ VOD VDDO out out LVDSDC Input ➤ VOS/Δ VOS VDDO LVCMOS OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPW tPERIOD tPW tPERIOD odc = x 100% nQC[0:2] tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA[0:2], QB[0:2] QC[0:2] LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PARAMETER MEASUREMENT INFORMATION, CONTINUED VOS 20% 80% 80% 20% tR tF VOD GND 20% 80% 80% 20% tR tF QA[0:2], QB[0:2], REF_OUT nQC[0:2] QC[0:2]

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

100 Ohm Differiential Transmission Line

FIGURE 5. P .C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) Figure 5. The the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. land pattern must be connected to ground through these vias. Electrically Enhance Leadfame Base Package, Amkor T echnology.

IDT™ / ICS™ LVDS/LVCMOS CLOCK GENERATOR 12 ICS8402010AKI REV. A AUGUST 28, 2008 ICS8402010I FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8402010I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8402010I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation

  • Power (core, output) = V DD_MAX * (I DD + I DDO_X + I DDA ) = 3.465V * (25mA + 30mA + 15mA) = 242.6mW LVCMOS Output Power Dissipation
  • Output Impedance R OUT Power Dissipation due to Loading 50 Ω to V DDO Output Current I OUT = VDDO_MAX / [2 * (50 Ω + ROUT)] = 3.465V / [2 * (50 Ω + 20Ω)] = 24.7mA
  • Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 Ω * (24.7mA) 2 = 12.25mW per output
  • Total Power Dissipation on the R OUT Total Power (ROUT) = 12.25mW * 6 = 73.5mW Total Power Dissipation
  • Total Power = Power (core, output) + Power Dissipation (R OUT) = 242.6mW + 73.5mW = 316.1mW

TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 32-LEAD VFQFN, FORCED CONVECTION Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per T able 6. flow, and the type of board.

TABLE 7. θ

TABLE 7. PACKAGE DIMENSIONS this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 8. ORDERING INFORMATION

FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA