SN54ALS74A_08 TI | Alldatasheet
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Technical content
/C0083/C0078/C0053/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0053/C0052/C0065/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0083/C0055/C0052/C0065 /C0068/C0085/C0065/C0076/C0032/C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0067/C0076/C0069/C0065/C0082/C0032/C0065/C0078/C0068/C0032/C0080/C0082/C0069/C0083/C0069/C0084 SDAS143C − APRIL 1982 − REVISED AUGUST 1995 Copyright 1995, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF) (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) ′ALS74A 50 6 ′AS74A 134 26
description
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE ) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of −55°C to 125 °C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H LXXL H L LXX H † H † H H ↑ HH L H H ↑ LL H H H L X Q 0 Q 0 † The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. SN54ALS74A, SN54AS74A ...J PACKAGE SN74ALS74A, SN74AS74A ...D O R N PACKAGE (TOP VIEW) 1CLR 1CLK 1PRE GND VCC 2CLR 2CLK 2PRE SN54ALS74A, SN54AS74A . . . FK PACKAGE (TOP VIEW) 3212 0 1 9 91 01 11 2 1 3 NC 2CLK NC 2PRE 1CLK NC 1PRE NC 1CLR NC V 2CLR NC CC NC − No internal connection GND /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0053/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0053/C0052/C0065/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0083/C0055/C0052/C0065 /C0068/C0085/C0065/C0076/C0032/C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0067/C0076/C0069/C0065/C0082/C0032/C0065/C0078/C0068/C0032/C0080/C0082/C0069/C0083/C0069/C0084 SDAS143C − APRIL 1982 − REVISED AUGUST 1995
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 logic symbol† S 1CLK R 2CLK 1PRE 2PRE 1CLR 2CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) PRE CLR Q Q CLK D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
/C0083/C0078/C0053/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0053/C0052/C0065/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0083/C0055/C0052/C0065 /C0068/C0085/C0065/C0076/C0032/C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0067/C0076/C0069/C0065/C0082/C0032/C0065/C0078/C0068/C0032/C0080/C0082/C0069/C0083/C0069/C0084 SDAS143C − APRIL 1982 − REVISED AUGUST 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions SN54ALS74A SN74ALS74A UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA fclock Clock frequency 0 25 0 34 MHz PRE or CLR low 15 15 tw Pulse duration CLK high 17.5 14.5 nstw Pulse duration CLK low 17.5 14.5 ns tsu Setup time before CLK↑ Data 16 15 nstsu Setup time before CLK↑ PRE or CLR inactive 10 10 ns th Hold time after CLK↑ Data 2 0 ns TA Operating free-air temperature −55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS74A SN74ALS74A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = −18 mA −1.5 −1.5 V VOH VCC = 4.5 V to 5.5 V,IOH = −2 mA VCC −2 VCC −2 V VOL VCC = 4.5 V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL VCC = 4.5 V IOL = 8 mA 0.35 0.5 V II CLK or D VCC = 4.5 V, VI = 7 V 0.1 0.1 mAII PRE or CLR VCC = 4.5 V, VI = 7 V 0.2 0.2 mA IIH CLK or D VCC = 4.5 V, VI = 2.7 V 20 20 AIIH PRE or CLR VCC = 4.5 V, VI = 2.7 V 40 40 µA IIL CLK or D VCC = 4.5 V, VI = 0.4 V −0.2 −0.2 mAIIL PRE or CLR VCC = 4.5 V, VI = 0.4 V −0.4 −0.4 mA IO ‡ VCC = 5.5 V, VO = 2.25 V −20 −112 −30 −112 mA ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded.
/C0083/C0078/C0053/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0053/C0052/C0065/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0083/C0055/C0052/C0065 /C0068/C0085/C0065/C0076/C0032/C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0067/C0076/C0069/C0065/C0082/C0032/C0065/C0078/C0068/C0032/C0080/C0082/C0069/C0083/C0069/C0084 SDAS143C − APRIL 1982 − REVISED AUGUST 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω, TA = MIN to MAX† UNITPARAMETER (INPUT) (OUTPUT) SN54ALS74A SN74ALS74A UNIT MIN MAX MIN MAX fmax 25 34 MHz tPLH PRE or CLR Q or Q 3 18 3 13 nstPHL PRE or CLR Q or Q 5 17 5 15 ns tPLH CLK Q or Q 5 23 5 16 ns tPHL CLK Q or Q 5 20 5 18 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS74A SN74AS74A UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −2 −2 mA IOL Low-level output current 20 20 mA fclock* Clock frequency 0 90 0 105 MHz PRE or CLR low 4 4 tw * Pulse duration CLK high 4 4 nstw * Pulse duration CLK low 5.5 5.5 ns tsu* Setup time before CLK↑ Data 4.5 4.5 nstsu* Setup time before CLK↑ PRE or CLR inactive 2 2 ns th* Hold time after CLK↑ Data 0 0 ns TA Operating free-air temperature −55 125 0 70 °C * On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested.
/C0083/C0078/C0053/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0053/C0052/C0065/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0076/C0083/C0055/C0052/C0065/C0044/C0032/C0083/C0078/C0055/C0052/C0065/C0083/C0055/C0052/C0065 /C0068/C0085/C0065/C0076/C0032/C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068/C0032/C0068/C0262/C0084/C0089/C0080/C0069/C0032/C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072/C0032/C0067/C0076/C0069/C0065/C0082/C0032/C0065/C0078/C0068/C0032/C0080/C0082/C0069/C0083/C0069/C0084 SDAS143C − APRIL 1982 − REVISED AUGUST 1995 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS74A SN74AS74A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V VOH VCC = 4.5 V to 5.5 V,IOH = −2 mA VCC −2 VCC −2 V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH CLK or D VCC = 5.5 V, VI = 2.7 V 20 20 AIIH PRE or CLR VCC = 5.5 V, VI = 2.7 V 40 40 µA IIL CLK or D VCC = 5.5 V, VI = 0.4 V −0.5 −0.5 mAIIL PRE or CLR VCC = 5.5 V, VI = 0.4 V −1.8 −1.8 mA IO ‡ VCC = 5.5 V, VO = 2.25 V −30 −112 −30 −112 mA ICC VCC = 5.5 V, See Note 1 10.5 16 10.5 16 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω, TA = MIN to MAX§ UNITPARAMETER (INPUT) (OUTPUT) SN54AS74A SN74AS74A UNIT MIN MAX MIN MAX fmax * 90 105 MHz tPLH PRE or CLR Q or Q 2 9 2 7.5 nstPHL PRE or CLR Q or Q 2.5 11.5 2.5 10.5 ns tPLH CLK Q or Q 2.5 10 3 8 ns tPHL CLK Q or Q 3.5 10.5 3 9 ns * On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested. § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9862701Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-9862701QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 84011012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 8401101CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 8401101DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type JM38510/37101B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type JM38510/37101BCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SN54ALS74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SN54AS74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SN74ALS74AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74AJ OBSOLETE CDIP J 14 TBD Call TI Call TI SN74ALS74AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS74AN3 OBSOLETE PDIP N 14 TBD Call TI Call TI SN74ALS74ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS74ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 1
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74AS74ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AS74ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54ALS74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54ALS74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54ALS74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type SNJ54AS74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54AS74AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS74ADR SOIC D 14 2500 346.0 346.0 33.0 SN74ALS74ANSR SO NS 14 2000 346.0 346.0 33.0 SN74AS74ADR SOIC D 14 2500 346.0 346.0 33.0 SN74AS74ANSR SO NS 14 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96
28 TERMINAL SHOWN
B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
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