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Document overview
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Technical content
Features
- Four LVCMOS / LVTTL outputs
- Selectable crystal oscillator interface or LVCMOS / LVTTL single-ended clock input
- Supports the following output frequency: 125MHz
- RMS phase jitter @125MHz (1.875MHz - 20MHz): 0.6ps (typical)
- Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Phase Detector VCO M = ÷25 (fixed) N = ÷5 OSC OE nPLL_SEL nXTAL_SEL XTAL_IN XTAL_OUT TEST_CLK MR Pullup Pulldown Pulldown Pulldown Pulldown 25MHz 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2, 9, 20 nc Unused No connect pins. 3 nXTAL_SEL Input Pulldown PLL reference select control input. See Table 3A. LVCMOS/LVTTL interface levels. 4T E ST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5 OE Input Pullup Output enable control pin. See Table 3B. LVCMOS/LVTTL interface levels. 6 MR Input Pulldown Master reset control pin. See Table 3C. LVCMOS/LVTTL interface levels. 7n P L L _ SEL Input Pulldown PLL bypass control input. See Table 3D. LVCMOS/LVTTL interface levels. 8 VDDA Power Analog supply pin. 10 V DD Power Core supply pin. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 13, 19 GND Power Power supply ground. Q0 Output Single-ended clock outputs. 17 output impedance. LVCMOS/LVTTL interface levels. 16 V DDO Power Output supply pin.
Rev C 4/3/15 3 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Function Tables Table 3A. nXTAL_SEL PLL Reference Select Function Table Table 3B. Output Enable Function Table Table 3C. Master Reset Function Table Table 3D. PLL Bypass Function Table nXTAL_SEL PLL Reference Input 0 (default) XTAL Interface 1T E ST_CLK OE Output Operation 0 Q[0: 3] are disabled in high-impedance state. 1 (default) Q[0: 3] are enabled. MR Reset Operation 0 (default) Normal operation, internal dividers are enabled. 1 Internal dividers are reset, Q[0: 3] are disabled in logic low state. nPLL_SEL PLL Operation 0 (default) PLL is enabled 1 PLL is bypassed. The output frequency is equal to the selected reference frequency divided by the output divider of 5.
Rev C 4/3/15 4 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5% , TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Table 4C. Power Supply DC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 86.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.33 .465 V VDDA Analog Supply Voltage V DD – 0.14 3.3 VDD V VDDO Output Supply Voltage 3.135 3.33 .465 V IDD Core Supply Current 90m A IDDA Analog Supply Current 14 mA IDDO Output Supply Current No Load 8 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.33 .465 V VDDA Analog Supply Voltage V DD – 0.14 3.3 VDD V VDDO Output Supply Voltage 2. 375 2.5 2.625 V IDD Core Supply Current 90m A IDDA Analog Supply Current 14 mA IDDO Output Supply Current No Load 8 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2. 375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.14 2.5 V DD V VDDO Output Supply Voltage 2. 375 2.5 2.625 V IDD Core Supply Current 90m A IDDA Analog Supply Current 14 mA IDDO Output Supply Current No Load 8 mA
Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
Rev C 4/3/15 6 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with crystal input. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to phase noise plots. Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with crystal input. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to phase noise plots. Table 6C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with crystal input. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to phase noise plots. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 125 MHz tsk(o) Output Skew; NOTE 1, 2 20 60 ps tjit(Ø) RM S Phase Jitter (Random); NOTE 3 125MHz, Integration Range: 1.875MHz – 20MHz 0.604 ps tLOCK PLL Lock Time 50 100 ms tR / tF Output Rise/Fall Time 20% to 80% 250 400 750 ps odc Output Duty Cycle 42 50 5 8 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 125 MHz tsk(o) Output Skew; NOTE 1, 2 20 60 ps tjit(Ø) RM S Phase Jitter (Random); NOTE 3 125MHz, Integration Range: 1.875MHz – 20MHz 0.546 ps tLOCK PLL Lock Time 50 100 ms tR / tF Output Rise/Fall Time 20% to 80% 250 400 750 ps odc Output Duty Cycle 46 50 54 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 125 MHz tsk(o) Output Skew; NOTE 1, 2 20 60 ps tjit(Ø) RM S Phase Jitter (Random); NOTE 3 125MHz, Integration Range: 1.875MHz – 20MHz 0.544 ps tLOCK PLL Lock Time 50 100 ms tR / tF Output Rise/Fall Time 20% to 80% 250 400 750 ps odc Output Duty Cycle 42 50 5 8 %
Rev C 4/3/15 7 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Typical Phase Noise at 125MHz (3.3V/3.3V) Typical Phase Noise at 125MHz (3.3V/2.5V) Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz
Rev C 4/3/15 8 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Typical Phase Noise at 125MHz (2.5V/2.5V) Offset Frequency (Hz) Noise Power dBc Hz
Rev C 4/3/15 9 FEMTOCLOCK® CR YSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit Output Skew 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO 1.65V±5% VDDA SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO 1.25V±5% VDDA tsk(o) VDDO VDDO Qx Qy SCOPE Qx GND VDD 1.25V±5% -1.25V±5% VDDO 2.05V±5% VDDA 2.05V±5% Q[0:3] tPERIOD tPW tPERIOD odc = VDDO x 100% tPW
Rev C 4/3/15 10 FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Parameter Measurement Information, continued Output Rise/Fall Time Applications Information Recommendations for Unused Input and Output Pins Inputs: TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached. 20% 80% 80% 20% tR tF Q[0:3]
22pF and C2 = 22pF are recommended for frequency accuracy. used. This will required adjusting C1 and C2. supplies to isolate from coupling into the internal PLL. Figure 2. 840024I Application Schematic filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. suggests adding bulk capacitances in the local area of all devices.
28 MHz
characterized with all outputs terminated.
This section provides information on power dissipation and junction temperature for the 840024I. Equations and example calculations are also provided. The total power dissipation for the 840024I is the sum of the core power plus the analog power plus the output power dissipated into the load. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 86.7°C/W per Table 7 below. Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP
Rev C 4/3/15 15 FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET
Ordering Information
Table 10. Ordering Information
Rev C 4/3/15 16 FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840024I DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B 1 Block Diagram - corrected nXTAL_ SEL to select XTAL when LOW (0) and select TEST_CLK when HIGH (1). 8/30/2012 C 4A - 4C 6A - 6C Output Supply Current, Test Conditions: Added ‘No Load’. Added NOTE: Use XTAL input. 12/6/12 C Deleted 17 Output Impedance. RMS Phase Jitter from 0.604ps to 0.6ps IDDA from 12mA to 14mA Deleted NOTE: Use XTAL input. Added NOTE: Characterized with crystal input. Updated Power Considerations for 14mA 1/11/13 C Updated data sheet format. 4/ 3/15
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