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Technical content

Features

  • One LVCMOS/LVTTL outputs, 20 output impedance
  • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal
  • Output frequencies: 125MHz or 62.5MHz
  • RMS phase jitter at 125MHz using a 25MHz crystal (12kHz - 20MHz): 0.57ps (typical)
  • Supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Function Table Inputs Output Frequency Range (with a 25MHz crystal)FREQ_SEL 0 125MHz 1 62.5MHz OSC Phase Detector VCO M = ÷25 (fixed) 1÷10 Q XTAL_IN XTAL_OUT FREQ_SEL Pulldown PWR_DN Pullup 25MHz 5 6 7 8 16 15 14 13 PWR_DN XTAL_OUT XTAL_IN GND Q nc VDDO VDD GND nc FREQ_SEL GND nc nc GND VDD ICS840022I-02

16 Lead VFQFN

Pin AssignmentBlock Diagram

ICS840022AKI-02 May 27, 2017 2 ©2017 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. PWR_DN Function Table 1 PWR_DN Input Pullup Output state control pin. See Table 3. LVCMOS/LVTTL interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 4, 5, 8, 13 GND Power Power supply ground. 6, 11, 14, 15 nc Unused No connect. 7 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 9, 16 V DD Power Power supply pins. 10 V DDO Power Output supply pin. 12 Q Output Single-ended clock output. 20 typical output impedance. LVCMOS/LVTTL interface levels.

0 Output in High-Impedance

1 Output in normal operation

ICS840022AKI-02 May 27, 2017 3 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 74.9C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current PWR_DN = 1 77 mA PWR_DN = 0 <1 mA IDDO Output Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current PWR_DN = 1 68 mA PWR_DN = 0 <1 mA IDDO Output Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current PWR_DN = 1 77 mA PWR_DN = 0 <1 mA IDDO Output Supply Current 10 mA

ICS840022AKI-02 May 27, 2017 4 ©2017 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 5. Crystal Characteristics

ICS840022AKI-02 May 27, 2017 5 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plot. Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plot. Table 6C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 125 MHz FREQ_SEL = 1 62.5 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, Integration Range: 12kHz – 20MHz 0.57 ps 62.5MHz, Integration Range: 12kHz – 10MHz 0.58 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 125 MHz FREQ_SEL = 1 62.5 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 125MHz, Integration Range: 12kHz – 20MHz 0.62 ps 62.5MHz, Integration Range: 12kHz – 10MHz 0.58 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency FREQ_SEL = 0 125 MHz FREQ_SEL = 1 62.5 MHz tjit(Ø) RMS Phase Jitter, Random 125MHz, Integration Range: 12kHz – 20MHz 0.62 ps 62.5MHz, Integration Range: 12kHz – 10MHz 0.58 ps tR / tF Output Rise/Fall Time 20% to 80% 200 750 ps odc Output Duty Cycle 47 53 %

ICS840022AKI-02 May 27, 2017 6 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Typical Phase Noise at 62.5MHz (3.3V) Typical Phase Noise at 125MHz (3.3V) Gb Ethernet Filter Phase Noise Result by adding a Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 12kHz to 10MHz = 0.58ps (typical) Offset Frequency (Hz) Noise Power dBc Hz Gb Ethernet Filter Phase Noise Result by adding a Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.57ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

ICS840022AKI-02 May 27, 2017 7 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Parameter Measurement Information 3.3V LVCMOS Output Load AC Test Circuit 2.5V LVCMOS Output Load AC Test Circuit Output Rise/Fall Time 3.3V/2.5V LVCMOS Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE QLVCMOS GND VDD, VDDO 1.65V±5% -1.65V±5% SCOPE QLVCMOS GND VDD, VDDO 1.25V±5% -1.25V±5% 20% 80% 80% 20% tR tF Q SCOPE Q LVCMOS GND 2.05V±5% -1.25V±5% VDD VDDO 1.25V±5% Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q

ICS840022AKI-02 May 27, 2017 9 ©2017 Integrated Device Technology, Inc. resistance is not required but can be added for additional protection. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS840022AKI-02 May 27, 2017 10 ©2017 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN

ICS840022AKI-02 May 27, 2017 11 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package Outline Drawings (Sheet 1)

ICS840022AKI-02 May 27, 2017 12 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package Outline Drawings (Sheet 2)

ICS840022AKI-02 May 27, 2017 13 ©2017 Integrated Device Technology, Inc. ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS840022I-02 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR 14©2017 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual p roperty rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Revision History Sheet Rev Table Page Description of Change Date A 1 Corrected Block Diagram. Updated VFQFN EPAD Thermal Release Path section. 11/7/07 B T4C T6C Features Section - added 3.3V/2.5V operating supply. Added 3.3V/2.5V Power Supply DC Characteristics Table. Added 3.3V/2.5V Power Supply AC Characteristics Table. Added 3.3V/2.5V Output Load AC Test Circuit diagram. Updated Overdriving the Crystal Interface. Updated Package Drawing. Converted datasheet format. 7/28/10 C - 11/12 Updated the package outline drawings. 5/27/2017