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Technical content
Features
- One 65.536MHz output, synchronized to 8kHz reference
- One 25MHz output, buffered version of the internal osc output
- Provides lock and reference fail indication
- Free run mode when reference clock (REF) fails
- Automatic switch-over to reference when good reference (REF) is available
- 25MHz external master clock source: crystal or oscillator
- Full 3.3V operation
- -40°C to 85°C ambient operating temperature
- Available in a lead-free (RoHS 6) package 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc C25o GND REF nc VDD GND nc nc nc VDD FIL_OUT VDD OSCi OSCo nRST nc LOCK REF_FAIL GND GND nc nc GND nc nc VDDA nc C65o VDDA nc nc OSC PLL C65o C25o Pulldown Pullup 25MHz OSCo REF nRST OSCi Reference Monitor Lock Detector REF_FAIL LOCK FIL_OUT ÷3125 8400110 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View Pin AssignmentBlock Diagram 8400110 Datasheet Low Jitter, Telecom Rate-Conversion PLL
8400110 Datasheet
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics reference. LVCMOS/LVTTL interface levels.
3 REF_FAIL Output
(REF) frequency is exhibiting abrupt phase or frequency change. LVCMOS/LVTTL interface levels. 4, 5, 8, 27, 31 GND Power Power supply ground. forced into high-impedance. LVCMOS/LVTTL interface levels. 11 OSCi Input Crystal in or single ended clock input. 12, 14, 30 V DD Power Core supply pins. 13 FIL_OUT Output Filter output pi n connected to 4.7µF capacitor. 18, 21 V DDA Power Analog supply pins. general TDM applications. LVCMOS/LVTTL interface levels.
26 C25o Output
that of the external crystal or oscillator. LVCMOS/LVTTL interface levels.
3©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 The PLL of 8400110 consists of a phase detector, a loop filter and a Voltage Controlled Oscillator (VCO). In the normal mode of operation, the VCO provides an output clock signal that is frequency and phase locked to the input reference clock (REF). In free-run mode, VCO is locked to 25MHz input with an accuracy equal to the accuracy of the OSCi 25MHz clock. Lock Indicator The Lock detector monitors if the output clock phase is within 90° of the input reference (REF). If the difference between input reference clock (REF) and output is more than 90°, LOCK output is LOW. The monitor than looks for eight consecutive clocks within 22.5° of the reference, before setting the LOCK to a HIGH. REF_FAIL The REF_FAIL signal is HIGH when reference clock (REF) shows greater than 130ppm variation in frequency, there are more than three consecutive edges missing, or there is an abrupt phase shift in the reference clock REF . Under any of these circumstances the PLL input will be switched from primary reference clock (REF) to crystal. When the primary reference clock (REF) is restored and REF_FAIL sets to LOW, the PLL input is switched back to the primary reference clock (REF). Modes of Operation The 8400110 device has two modes of operation; normal mode and free-run mode. The device powers up in free-run mode, it automatically transitions to normal mode if a valid reference clock (REF) is available and transitions to free-run mode if the reference fails. RESET signal also will puts the device in free-run mode. Freerun Mode The freerun mode is typically used when an asynchronous clock source is required or it is used immediately following system power-up before synchronization is achieved. In free-run mode, 8400110 provides an output clock based on oscillator frequency. The output is not synchronized to the reference input clock (REF). In the free-run mode the accuracy of output frequency is equal to the accuracy of the frequency of the oscillator. Normal Mode The normal mode is typically used when a synchronous clock is required. In normal mode, 8400110 provides an output clock which is synchronized to the input (REF). Lock Time This is the time it takes the PLL to lock to the input reference clock REF . Lock occurs when the input signal and output signal are aligned in phase and frequency with respect to each other. LOCK time is affected by many factors which include: - Initial input to output phase difference - Initial input to output frequency difference - PLL loop bandwidth
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. Table 4. Crystal Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C has been reached under these conditions. Table 6. Functional Performance Characteristics has been reached under these conditions. NOTE 1: Peak-to-Peak jitter was calculated with RMS Period jitter data multiplied by BER 14.
6©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Parameter Measurement Information Output Load AC Test Circuit RMS Phase Jitter Output Pulse Width Cycle-to-Cycle Jitter Period Jitter Peak-to-Peak Output Rise/Fall Time SCOPE Qx LVCMOS GND VDD VDDA 1.65V±0.15V -1.65V±0.15V 1.65V±0.15V 1.65V±0.15V VDDA tPW tPERIOD VDDO VDDO VDDO tPW tPERIOD odc = C250, C650 C250, C650 ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
(First edge after trigger) 10,000 cycles Reference Point (Trigger Edge) Histogram t jit (pk-pk) 20% 80% 80% 20% tR tF C250, C650 NOTE: Using 30pF
7©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Parameter Measurement Information, continued Input-to-Output Timing for Synchronous Clock
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8400110 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering
values can be slightly adjusted for different board layouts. Figure 2. Crystal Input Interface Figure 3. The OSCo pin can be left floating. The input edge rate can attenuate the signal in half. This can be done in one of two ways. note, the device performance is guaranteed by using a quartz crystal. Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the 8400110. Equations and example calculations are also provided. DD = 3.3V + 0.3V = 3.6V, which gives worst case results. that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN
Table 9. Package Dimensions for 32 Lead VFQFN package dimensions are in Table 9.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
13©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016
Ordering Information
Table 10. Ordering Information
14©2016 Integrated Device Technology, Inc. Revision B, January 20, 2016 Rev Table Page Description of Change Date B T10 “General Description” - deleted HiperClocks logo. Ordering Information Table - deleted Tape & Reel count. Deleted all HiperClocks references throughout the datasheet. Deleted ICS prefix from part number throughout the datasheet. Updated datasheet header/footer. 1/20/16
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