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SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 Copyright 1995, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
- 3-State Buffer-Type Noninverting Outputs Drive Bus Lines Directly
- Bus-Structured Pinout
- Buffered Control Inputs
- SN74ALS575A and ′AS575 Have Synchronous Clear
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N, NT) and Ceramic (J, JT) 300-mil DIPs, and Ceramic Flat (W) Packages
description
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear (CLR ) input low. The output-enable (OE) input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C. OE GND VCC CLK SN54ALS574B, SN54AS574 ...J O R W PACKAGE SN74ALS574B, SN74AS574 . . . DW OR N PACKAGE (TOP VIEW) 321 2 0 1 9 9 10 11 1213 OE 7Q 1Q GND CLK VCC SN54ALS574B, SN54AS574 . . . FK PACKAGE (TOP VIEW) SN54AS575 . . . JT OR W PACKAGE SN74ALS575A, SN74AS575 . . . DW OR NT PACKAGE (TOP VIEW) CLR OE NC GND VCC NC CLK NC SN54AS575 ...F K PACKAGE (TOP VIEW) 321 13 14 NC NC 15 16 17 18 NC GND NC NC CLK OE CLR NC 28 27 2625 NC VCC NC – No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ LL L LX Q 0 H X X Z SN74ALS575A, SN54AS575, SN74AS575 (each flip-flop) INPUTS OUTPUT OE CLR CLK D Q L L ↑ X L L H ↑ HH L H ↑ LL L HLX Q 0 H X H X Z logic symbols† OE CLK EN OE CLK EN CLR 1R SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 SN74ALS575A, SN54AS575, SN74AS575 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, J, JT, N, and NT packages.
SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagrams (positive logic) OE CLK To Seven Other Channels OE CLK To Seven Other Channels SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 SN74ALS575A, SN54AS575, SN74AS575 CLR Pin numbers shown are for the DW, J, JT, N, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS574B SN74ALS574B SN74ALS575A UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA f lk Clock frequency ′ALS574B 0 28 0 35 MHzfclock Clock frequency SN74ALS575A 0 30 MH z t Pulse duration ′ALS574B, CLK high or low 16.5 14 nstw Pulse duration SN74ALS575A, CLK high or low 16.5 ns t Set p time before CLK↑ Data 15 15 nstsu Setup time before CLK ↑ SN74ALS575A, CLR 15 ns th Hold time after CLK↑ Data 4 0 nsth H old time after CLK ↑ SN74ALS575A, CLR 0 ns TA Operating free-air temperature –55 125 0 70 °C
SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS574B SN74ALS574B SN74ALS575A UNIT MIN TYP † MAX MIN TYP † MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V,IOH = –0.4 mA VCC –2 VCC –2 VOH VCC =45V IOH = –1 mA 2.4 3.3 V VCC = 4.5 V IOH = –2.6 mA 2.4 3.2 VOL VCC =45V IOL = 12 mA 0.25 0.4 0.25 0.4 VVOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V 20 20 µA IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –20 –1 12 –30 –1 12 mA Outputs high 11 18 11 18 ′ALS574B VCC = 5.5 V Outputs low 17 27 17 27 ICC Outputs disabled 17 28 17 28 mAICC Outputs high 10 17 10 17 mA SN74ALS575A VCC = 5.5 V Outputs low 15 24 15 24 Outputs disabled 16 30 16 30 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX§ UNIT SN54ALS574B SN74ALS574B SN74ALS575A MIN MAX MIN MAX MIN MAX fmax 28 35 30 MHz tPLH CLK Q 4 22 3 14 4 14 ns tPHL CLK Q 4 17 4 14 4 14 ns tPZH OE Q 4 21 3 18 4 18 ns tPZL OE Q 4 26 4 18 4 18 ns tPHZ OE Q 2 16 1 10 2 10 ns tPLZ OE Q 2 25 2 12 3 13 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS574 SN54AS575 SN74AS574 SN74AS575 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current 32 48 mA fclock* Clock frequency 0 100 0 90 MHz t * Pulse duration CLK high 5 5.5 nstw * Pulse duration CLK low 4 5.5 ns t * Set p time before CLK↑ Data 3 5.5 nstsu* Setup time before CLK ↑ ′AS575, CLR high or low 6.5 6.5 ns th* Hold time after CLK↑ Data 3 3 nsth* H old time after CLK ↑ ′AS575, CLR 0 0 ns TA Operating free-air temperature –55 125 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS574 SN54AS575 SN74AS574 SN74AS575 UNIT MIN TYP † MAX MIN TYP † MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V,IOH = –2 mA VCC –2 VCC –2 VOH VCC =45V IOH = –12 mA 2.4 3.2 V VCC = 4.5 V IOH = –15 mA 2.4 3.3 VOL VCC =45V IOL = 32 mA 0.29 0.5 VVOL VCC = 4.5 V IOL = 48 mA 0.34 0.5 V IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA IOZL VCC = 5.5 V, VO = 0.4 V –50 –50 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA IIL OE , CLK, CLR VCC =55V VI=04V –0.5 –0.5 mAIIL D VCC = 5.5 V, VI = 0.4 V –3 –2 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –30 –1 12 –30 –1 12 mA Outputs high 73 116 73 116 ′AS574 VCC = 5.5 V Outputs low 85 134 85 134 ICC Outputs disabled 84 134 84 134 mAICC Outputs high 78 126 78 126 mA ′AS575 VCC = 5.5 V Outputs low 89 142 89 142 Outputs disabled 88 142 88 142 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . switching characteristics (see Figure 1) PARAMETER FROM (INPUT ) TO (OUTPUT ) VCC = 4.5 V to 5.5 V, C L = 50 pF, R1 = 500 Ω , R2 = 500 Ω , TA = MIN to MAX§ UNIT(INPUT) (OUTPUT) SN54AS574 SN54AS575 SN74AS574 SN74AS575 MIN MAX MIN MAX fmax * 100 90 MHz tPLH CLK An Q 3 11 3 8 ns tPHL CLK Any Q 4 11 4 9 ns tPZH OE An Q 2 7 2 6 ns tPZL OE Any Q 3 11 3 10 ns tPHZ OE Any Q 2 7 2 6 ns tPLZ OE Any Q 2 7 2 6 ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms
www.ti.com 25-Sep-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 84001012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84001012A SNJ54ALS 574BFK 8400101RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8400101RA SNJ54ALS574BJ 8400101SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101SA SNJ54ALS574BW JM38510/37104B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37104B2A JM38510/37104BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 37104BRA M38510/37104B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37104B2A M38510/37104BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 37104BRA SN54ALS574BJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54ALS574BJ SN54AS574J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54AS574J SN54AS575JT OBSOLETE CDIP JT 24 TBD Call TI Call TI -55 to 125 SN74ALS574BDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BDWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS574BN SN74ALS574BN3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70
www.ti.com 25-Sep-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74ALS574BNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS574BN SN74ALS574BNSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BNSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS574BNSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B SN74ALS575ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS575A SN74ALS575ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS575A SN74ALS575ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS575A SN74ALS575ANT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS575ANT SN74ALS575ANTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS575ANT SN74AS574DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 SN74AS574N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS574N SN74AS574NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS574N SN74AS575DW OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70 SN74AS575DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70
www.ti.com 25-Sep-2013 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74AS575NT OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70 SNJ54ALS574BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84001012A SNJ54ALS 574BFK SNJ54ALS574BJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8400101RA SNJ54ALS574BJ SNJ54ALS574BW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101SA SNJ54ALS574BW SNJ54AS574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54AS 574FK SNJ54AS574J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54AS574J SNJ54AS575FK OBSOLETE LCCC FK 28 TBD Call TI Call TI -55 to 125 SNJ54AS575JT OBSOLETE CDIP JT 24 TBD Call TI Call TI -55 to 125 SNJ54AS575W OBSOLETE CFP W 24 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
www.ti.com 25-Sep-2013 Addendum-Page 4 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS574B, SN54AS574, SN54AS575, SN74ALS574B, SN74AS574, SN74AS575 :
- Catalog: SN74ALS574B , SN74AS574 , SN74AS575
- Military: SN54ALS574B , SN54AS574 , SN54AS575 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS574BDWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS574BNSR SO NS 20 2000 367.0 367.0 45.0 SN74AS574DWR SOIC DW 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2
MCER004A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
B 0.200 (5,08) MAX 0.320 (8,13) 0.290 (7,37) 0.130 (3,30) MIN 0.008 (0,20) 0.014 (0,36) Seating Plane 0.030 (0,76) 0.070 (1,78) 0.015 (0,38) MIN A 0.100 (2,54) MAX 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0°–15° 1.440 (37,08) 1.460 0.285 (7,39) 0.291 (36,58) (7,24) 28PINS ** 1.280 1.240 0.300 0.245 (7,62) DIM B MAX A MAX A MIN B MIN (6,22) (32,51) (31,50) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MCFP007 – OCTOBER 1994 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 4040180-5/B 03/95 1.115 (28,32) 0.090 (2,29) 0.375 (9,53) 0.019 (0,48) 0.030 (0,76) 0.045 (1,14) 0.006 (0,15) 0.045 (1,14) 0.015 (0,38) 0.015 (0,38) 0.026 (0,66) 0.004 (0,10) 0.340 (8,64) 0.840 (21,34) 12 4 0.360 (9,14) 0.240 (6,10) 1312 Base and Seating Plane 30° TYP 0.360 (9,14) 0.240 (6,10) 0.395 (10,03) 0.360 (9,14) 0.640 (16,26) 0.490 (12,45) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD E. Index point is provided on cap for terminal identification only.
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