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Technical content
Features
- Four single-ended LVCMOS/LVTTL outputs 17 typical output impedance
- Selectable crystal oscillator interface or single-ended input
- Output frequency range: 56MHz - 175MHz
- VCO range: 560MHz - 700MHz
- RMS phase jitter at 156.25MHz (1.875MHz – 20MHz): 0.52ps (typical) Phase Noise: Offset Noise Power 100Hz -94.9 dBc/Hz 1kHz -119.6 dBc/Hz 10kHz -128.9 dBc/Hz 100kHz -129.2 dBc/Hz
- Full 3.3V or mixed 3.3V core/2.5V output supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package Frequency Select Function Table for Ethernet Frequencies Inputs Output Frequency (MHz), (25MHz Reference)F_SEL1 F_SEL0 M Div. Value N Div. Value M/N Ratio Value 0 0 25 4 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 5 5 125 (default) nc VDDA nPLL_SEL MR OE REF_CLK nXTAL_SEL nc F_SEL0 VDD F_SEL1 GND VDDO GND XTAL_IN XTAL_OUTOSC Phase Detector VCO M = ÷25 (fixed) F_SEL1:0 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 ÷5 (default) N OE F_SEL1:0 nPLL_SEL nXTAL_SEL REF_CLK MR XTAL_IN XTAL_OUT Pullup Pulldown Pulldown Pulldown Pulldown 25MHz Pullup:Pullup 840004-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics F_SEL1 Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 4 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
6 MR Input Pulldown
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL bypass. When LOW, the output is driven from the VCO output. clock frequency/N output divider. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 10 V DD Power Core supply pin. 13, 19 GND Power Power supply ground. 14, 15, 17, 18 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 17 typical output impedance. LVCMOS/ LVTTL interface levels. 16 V DDO Power Output supply pin.
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage V DD = 3.465V 2 V DD + 0.3 V VIL Input Low Voltage V DD = 3.465V -0.3 0.8 V IIH Input High Current nXTAL_SEL, nPLL_SEL, REF_CLK, MR VDD = VIN = 3.465V 150 µA OE, F_SEL[0:1] V DD = VIN = 3.465V 5 µA IIL Input Low Current nXTAL_SEL, nPLL_SEL, REF_CLK, MR VDD = 3.465V, VIN = 0V -5 µA OE, F_SEL[0:1] V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VOL Output Low Voltage; NOTE 1 V DDO = 3.3V ± 5% or 2.5V ± 5% 0.5 V
Table 4. Crystal Characteristics thermal equilibrium has been reached under these conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots.
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Typical Phase Noise at 62.5MHz (3.3V) Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fout Output Frequency F_SEL[1:0] = 00 140 156.25 175 MHz F_SEL[1:0] = 01 or 11 112 125 140 MHz F_SEL[1:0] = 10 56 62.5 70 MHz tsk(o) Output Skew: NOTE 1, 2 60 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 3 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.48 ps 125MHz, Integration Range: 1.875MHz – 20MHz 0.59 ps 62.5MHz, Integration Range: 1.875MHz – 20MHz 0.53 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle F_SEL[1:0] = 00, 01 or 11 43 57 % 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
Rev B 4/2/15 6 FEMTOCLOCK™ CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840004-01 DATA SHEET Typical Phase Noise at 62.5MHz (2.5V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 125MHz (3.3V) Typical Phase Noise at 156.25MHz (3.3V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.65ps (typical) Offset Frequency (Hz) Noise Power dBc Hz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
Rev B 4/2/15 8 FEMTOCLOCK™ CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840004-01 DATA SHEET Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Output Skew Output Duty Cycle Pulse Width/Period 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO VDDA 1.65V±5% tsk(o) VDDO VDDO Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q3 SCOPE Qx GND VDD 1.25V±5% -1.25V±5% VDDO VDDA 2.05V±5% 2.05V±5% Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF Q0:Q3
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Application Information
Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The 840004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering
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the logic control input pins. Figure 4. P.C. 840004-01 Schematic Example If not using the crystal input, it can be left floating.
Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Ordering Information
Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev B 4/2/15 14 FEMTOCLOCK™ CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840004-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T5A, T5B 4 - 5 AC Characteristics Tables - revi sed Test Conditions for Output Duty Cycle. Updated format throughout datasheet. 10/30/08 Updated data sheet format. 4/2/15
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