840004 RENESAS | Alldatasheet

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  • Manufacturer or author: rdvorak
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FemtoClocks™ Crystal-to-LVCMOS/ LVTTL Frequency Synthesizer 840004 DATASHEET 840004 REVISION B 4/1/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 840004 is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 26.5625MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The 840004 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The 840004 is packaged in a small 20-pin TSSOP package. BLOCK DIAGRAM

FEATURES

 Four LVCMOS/LVTTL outputs, 17Ω typical output impedance  Selectable crystal oscillator interface or LVCMOS single-ended input  Supports the following input frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz  VCO range: 560MHz - 700MHz  RMS phase jitter @ 212.5MHz (637kHz - 10MHz): 0.49ps typical, V DDO = 3.3V Phase noise: Offset Noise Power  Full 3.3V or mixed 3.3V core/2.5V output supply mode  0°C to 70°C ambient operating temperature  Available in lead-free (RoHS 6) package OE F_SEL1:0 nPLL_SEL nXTAL_SEL XTAL_IN XTAL_OUT REF_CLK MR OSC Phase Detector VCO M = ÷24 (fixed) F_SEL1:0 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 (default) N 26.5625MHz Pullup Pulldown Pulldown Pulldown Pullup:Pullup Pulldown FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT 840004 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View F_SEL0 nc nXTAL_SEL REF_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND V DDO GND XTAL_IN XTAL_OUT Inputs Output Frequency Range (MHz)Input Frequency (MHz) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Ratio Value 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 (default) 26.04166 0 1 24 4 6 156.25

840004 DATA SHEET

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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. 4 REF_CLK Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. outputs are in a high impedance state. LVCMOS/LVTTL interface levels.

6 MR Input Pulldown

and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. clock frequency/N output divider. LVCMOS/LVTTL interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_OUT is the output. 13, 19 GND Power Power supply ground. Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 17Ω typical output impedance. 20 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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tended periods may affect product reliability. TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. /2. See Parameter Measurement Information, Output Load Test Circuit.

FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER

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TABLE 5A. AC CHARACTERISTICS, V DD = V DDA = V DDO = 3.3V±5%, TA = 0°C TO 70°C TABLE 5B. AC CHARACTERISTICS, V DD = V DDA = 3.3V±5%, V DDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 186.67 212.5 226.66 MHz F_SEL[1:0] = 01 140 159.375 170 MHz F_SEL[1:0] = 10 93.33 156.25 113.33 MHz F_SEL[1:0] = 11 46.67 106.25 56.66 MHz tsk(o) Output Skew; NOTE 1, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 212.5MHz (637kHz - 10MHz) 0.49 ps 159.375MHz (637kHz - 10MHz) 0.55 ps 156.25MHz (1.875MHz - 20MHz) 0.56 ps 106.25MHz (637kHz - 10MHz) 0.79 ps 53.125MHz (637kHz - 10MHz) 0.65 ps t R / t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle F_SEL[1:0] = 10 or 11 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO /2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 186.67 212.5 226.66 MHz F_SEL[1:0] = 01 140 159.375 170 MHz F_SEL[1:0] = 10 93.33 156.25 113.33 MHz F_SEL[1:0] = 11 46.67 106.25 56.66 MHz tsk(o) Output Skew; NOTE 1, 3 60 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 212.5MHz (637kHz - 10MHz) 0.46 ps 159.375MHz (637kHz - 10MHz) 0.54 ps 156.25MHz (1.875MHz - 20MHz) 0.57 ps 106.25MHz (637kHz - 10MHz) 0.73 ps 53.125MHz (637kHz - 10MHz) 0.63 ps t R / t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle F_SEL[1:0] = 10 or 11 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO /2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

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LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 53.125MHZ @3.3V -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 53.125MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.65ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.79ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter TYPICAL PHASE NOISE AT 106.25MHZ @3.3V 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M

FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER

6 REVISION B 4/1/15

212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.49ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter TYPICAL PHASE NOISE AT 212.5MHZ@ 3.3V 10 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 159.375MHZ @3.3V -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 159.375MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.55ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter 10 100 1k 10k 100k 1M 10M 100M

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LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT SKEW 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODOUTPUT RISE/FALL TIME 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER

8 REVISION B 4/1/15

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 840004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD , V DDA , and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V DDA POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING Figure 2. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.

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protection, a 1kΩ resistor can be tied from the REF_CLK to ground. resistance is not required but can be added for additional protection. Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE removing R1 and making R2 50Ω.

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FIGURE 4. 840004 SCHEMATIC EXAMPLE

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TABLE 6. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 7. PACKAGE DIMENSIONS

840004 D ATA SHEET

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TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/ LVTTL FREQUENCY SYNTHESIZER

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Rev Table Page Description of Change Date B T4 3 Crystal Table - added Frequency min/max values. 8/16/06 Updated data sheet format. 4/2/15

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