840004-11 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Integrated Device Technology
  • PDF pages: 14

Technical content

Features

  • Four single-ended LVCMOS/LVTTL outputs 17 typical output impedance
  • Crystal oscillator interface
  • Input frequency range: 22.4MHz to 28MHz
  • Output frequency range: 56MHz - 140MHz
  • VCO range: 560MHz - 700MHz
  • RMS phase jitter at 125MHz (1.875MHz – 20MHz): 0.70ps (typical) Phase Noise: Offset Noise Power 100Hz -95.5 dBc/Hz 1kHz -123.6 dBc/Hz 10kHz -132.8 dBc/Hz 100kHz -133.4 dBc/Hz
  • Full 3.3V output supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Frequency Select Function Table for Ethernet Frequencies Inputs Output Frequency (MHz), 25MHz ReferenceF_SEL M Divider Value N Divider Value 0 25 10 62.5 1 25 5 125 (default) nc VDDA nc nc OE nc nc nc F_SEL VDD nc GND VDDO GND XTAL_IN XTAL_OUT OSC VCO M = ÷25 (fixed) F_SEL 0 ÷10 1 ÷5 (default) NPhase Detector OE F_SEL XTAL_IN XTAL_OUT 25MHz Pullup Pullup ICS840004-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram 840004-11 Datasheet FemtoClock™ Crystal-to-LVCMOS/LVTTL Frequency Synthesizer

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 F_SEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 7, 9, 20 nc Unused No connect. outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 8V DDA Power Analog supply pin. 10 V DD Power Core supply pin. XTAL_IN Input Crystal oscillator interface. XTA L_IN is the input. XTAL_OUT is the output. 13, 19 GND Power Power supply ground. 14, 15, 17, 18 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 17 typical output impedance. LVCMOS/ LVTTL interface levels. 16 V DDO Power Output supply pin.

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots.

5©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet Typical Phase Noise at 62.5MHz 1Gb Ethernet Filter Phase Noise Result by adding a 1Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

6©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet Typical Phase Noise at 125MHz 1Gb Ethernet Filter Phase Noise Result by adding a 1Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.70ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

7©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Output Skew Output Duty Cycle Pulse Width/Period RMS Phase Jitter Output Rise/Fall Time SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO VDDA 1.65V±5% tsk(o) VDDO VDDO Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q3 Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF Q0:Q3

8©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet

Application Information

Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k  resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 840004-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

11©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet

Ordering Information

Table 8. Ordering Information

12©2015 Integrated Device Technology, Inc December 7, 2015 840004-11 Datasheet Revision History Sheet Rev Table Page Description of Change Date A AC Characteristics Tables - added Thermal note. Added LVCMOS to XTAL Interface section. Ordering Information Table - deleted “ICS” prefix from Part/Order Number column. Converted datasheet format. 9/16/09 A note below the table. Updated datasheet format. 12/7/15

DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2015 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com 840004-11 Datasheet

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.