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Technical content
Features
- T wo L VCMOS/L VTTL outputs@ 3.3V, 17 typical output impedance
- Selectable crystal oscillator interface or LVCMOS/L VTTL single-ended TEST_CLK
- Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz
- Output frequency range: 56MHz to 175MHz
- VCO range: 560MHz to 700MHz
- Output skew: 12ps (maximum)
- RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz): 0.47ps (typical) Phase Noise: Offset Noise Power
- Power Supply Modes: Core / Output 3.3V / 3.3V 3.3V / 2.5V 2.5V / 2.5V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Inputs Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 F_SEL1 GND GND VDDO XTAL_IN XTAL_OUTVDD VDDA nPLL_SEL MR OE TEST_CLK nXTAL_SEL F_SEL0 Pin Assignment OSC Phase Detector VCO M = 25 (fixed) F_SEL1:0 00 4 01 5 10 1 0 11 5 N OE F_SEL1:0 nPLL_SEL nXT AL_SEL XT AL_IN XT AL_OUT TEST_CLK MR Pullup Pullup:Pullup Pulldown Pulldown Pulldown Pulldown 840002I-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View Block Diagram
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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See T able 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 3 TEST_CLK Input Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels. outputs are in high-impedance state. LVCMOS/LVTTL interface levels.
5 MR Input Pulldown
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. frequency/N output divider. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 8V DD Power Core supply pin. 11 V DDO Power Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. 16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
Rev B 8/5/15 3 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD =V DDA = 3.3V±5%, V DDO = 3.3V±5% or 2.5V±5%, T A = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VDD =V DDA =V DDO = 2.5V±5%, T A = -40°C to 85°C Item Rating Supply Voltage, V DD 4.6V Inputs, V I XTAL_IN Other Inputs 0V to V DD -0.5V to V DD + 0.5V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, T STG -65Ct o1 5 0 C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 95 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 5m A
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NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load T est Circuit diagrams. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
Rev B 8/5/15 5 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Table 5A. AC Characteristics, VDD =V DDA =V DDO = 3.3V±5%, T A = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to Phase Noise Plots. Table 5B. AC Characteristics, VDD =V DDA = 3.3V±5%, V DDO = 2.5V±5%, T A = -40°C to 85°C For NOTES, see T able 5A above. Table 5C. AC Characteristics, VDD =V DDA =V DDO = 2.5V±5%, T A = -40°C to 85°C For NOTES, see T able 5A above. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz tsk(o) Output Skew; NOTE 1, 2 12 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 156.25MHz, (1.875MHz - 20MHz) 0.47 ps 125MHz, (1.875MHz - 20MHz) 0.57 ps 62.5MHz, (1.875MHz - 20MHz) 0.51 ps tR /t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 46 54 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz tsk(o) Output Skew; NOTE 1, 2 12 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 156.25MHz, (1.875MHz - 20MHz) 0.47 ps 125MHz, (1.875MHz - 20MHz) 0.55 ps 62.5MHz, (1.875MHz - 20MHz) 0.49 ps tR /t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 46 54 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz tsk(o) Output Skew; NOTE 1, 2 12 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 3 156.25MHz, (1.875MHz - 20MHz) 0.49 ps 125MHz, (1.875MHz - 20MHz) 0.56 ps 62.5MHz, (1.875MHz - 20MHz) 0.52 ps tR /t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 46 54 % fOUT = 125MHz 47 53 %
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 62.5MHz (3.3V) 1Gb Ethernet Filter Phase Noise Result by adding a 1Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
Rev B 8/5/15 7 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Typical Phase Noise at 156.25MHz (3.3V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Parameter Measurement Information 3.3V Core/3.3V Output Load AC Test Circuit 2.5V Core/2.5V Output Load AC Test Circuit Output Skew 3.3V Core/2.5V Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDA, VDDO SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDA, VDDO tsk(o) VDDO VDDO Qx Qy SCOPE Qx LVCMOS VDDO GND VDD, VDDA VDDO 2.05V±5% -1.25V±5% 1.25V±5% Phase Noise Mas k Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:1] 20% 80% 80% 20% tR tF Q[0:1]
Rev B 8/5/15 9 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Applications Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XT AL_IN and XT AL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XT AL_IN to ground. TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A1 k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached.
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Overdriving the XTAL Interface The XT AL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XT AL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100 . This can also be accomplished by removing R1 and making R2 50 . By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
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Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP
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Ordering Information
Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Rev Table Page Description of Change Date number, marking and note. 10/18/07 AT 8 1 2 Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. 11/18/10 A T5A - T5C 4 - 5 AC Characteristics Tables - added thermal note. Power Supply Filtering Techniques - corrected figure 1. Added Overdriving the Crystal Interface section. Added Recommendations for Unused Input & Output Pins section. 12/6/10 B T5B T5C 3.3V/2.5V AC Characteristics Table -corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max. 2.5V AC Characteristics Table - added 2nd odc spec and added thermal note. Corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max. Deleted Power Supply Filtering Techniques section, added to schematic layout. Deleted Crystal Input Interface section. Added Overdriving the XTAL Interface section. Updated Layout Guideline and diagram. Converted datasheet format. 2/3/11 B 5A, 5B, 5C 5 AC Table; f OUT = F_SEL[1:0] = 01 or 11, F_SEL[1:0] = 10 9/28/12 B 8 13 Deleted Quantity from T ape and Reel Updated data sheet format. 8/5/15
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