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FEMTOCLOCKS™ Crystal-to-LVCMOS/ LVTTL Frequency Synthesizer 840002 DATASHEET 840002 REVISION C NOVEMBER 10, 2014 1 ©2014 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 840002 is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel reference clock frequencies. Using a 26.5625MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): The 840002 uses low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The 840002 is packaged in a 16-pin TSSOP package. BLOCK DIAGRAM P IN ASSIGNMENT F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD F_SEL1 GND GND V DDO XTAL_IN XTAL_OUT 840002 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View

FEATURES

 Two LVCMOS outputs @ 3.3V, 17Ω typical output imped- ance  Selectable crystal oscillator interface or LVCMOS single-ended input  Output frequency range: 46.66MHz - 233.33MHz  VCO range: 560MHz - 700MHz  Supports the following output frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz  RMS phase jitter @ 212.5MHz (637kHz - 10MHz): 0.83ps (typical) Typical phase noise at 212.5MHz: Offset Noise Power  Full 3.3V or 3.3V core/2.5V output supply modes  0°C to 70°C ambient operating temperature  Available in lead-free RoHS compliant package OE F_SEL1:0 nPLL_SEL nXTAL_SEL XTAL_IN XTAL_OUT TEST_CLK MR OSC Phase Detector VCO M = ÷24 (fixed) F_SEL1:0 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 (default) N 26.5625MHz Pullup Pulldown Pulldown Pulldown Pullup:Pullup Pulldown FREQUENCY SELECT FUNCTION TABLE FOR FIBRE CHANNEL APPLICATIONS Input Frequency (MHz) Inputs Output Frequency (MHz)F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Ratio Value 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25

840002 DATA SHEET

2 REVISION C 11/10/14

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. FREQUENCY SELECT FUNCTION TABLE 1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 3 TEST_CLK Input Pulldown Single-ended LVCMOS/LVTTL clock input. outputs are in a high impedance state. LVCMOS/LVTTL interface levels.

5 MR Input Pulldown

dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. clock frequency/n output divider. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 8V DD Power Core supply pin. XTAL_IN Input Crystal oscillator interface. 11 V DDO Power Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. 16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/

conditions for extended periods may affect product reliability. TABLE 5. CRYSTAL CHARACTERISTICS NOTE 1: Outputs terminated with 50W to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. NOTE: Characterized using an 18pf parallel resonant crystal.

FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/ LVTTL FREQUENCY SYNTHESIZER

4 REVISION C 11/10/14

TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 186.67 226.67 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.67 MHz tsk(o) Output Skew; NOTE 1, 3 12 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 212.5MHz @ Integration Range: 637kHz - 10MHz 0.83 ps 159.375MHz @ Integration Range: 637kHz - 10MHz 0.62 ps 156.25MHz @ Integration Range: 1.875MHz - 20MHz 0.59 ps 106.25MHz @ Integration Range: 637kHz - 10MHz 0.80 ps 53.125MHz @ Integration Range: 637kHz - 10MHz 0.68 ps t R / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle F_SEL[1:0] ¹ 00 46 54 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 186.67 226.67 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.67 MHz tsk(o) Output Skew; NOTE 1, 3 12 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 212.5MHz @ Integration Range: 637kHz - 10MHz 0.73 ps 159.375MHz @ Integration Range: 637kHz - 10MHz 0.62 ps 156.25MHz @ Integration Range: 1.875MHz - 20MHz 0.56 ps 106.25MHz @ Integration Range: 637kHz - 10MHz 0.76 ps 53.125MHz @ Integration Range: 637kHz - 10MHz 0.72 ps t R / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle F_SEL[1:0] ¹ 00 46 54 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.

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LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 53.125MHZ @3.3V0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 53.125MHz RMS Phase Jitter (Random) 637KHz to 10MHz = 0.68ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 212.5MHZ @3.3V0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 212.5MHz RMS Phase Jitter (Random) 637KHz to 10MHz = 0.83ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding Fibre Channel to raw data Raw Phase Noise Data Fibre Channel Filter 100 1k 10k 100k 1M 10M 100M

FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/ LVTTL FREQUENCY SYNTHESIZER

6 REVISION C 11/10/14

PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

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LVTTL FREQUENCY SYNTHESIZER

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 840002 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, V DDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V DDA. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING Figure 2. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.

8 REVISION C 11/10/14

FIGURE 3. 840002 SCHEMATIC EXAMPLE can be used for the logic control input pins. characterized with all outputs terminated. If not using the crystal input, it can be left floating. tied from XTAL_IN to ground. 1kΩ resistor can be tied from the TEST_CLK to ground. protection. A 1kΩ resistor can be used. that there is no trace attached.

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TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

10 REVISION C 11/10/14

TABLE 8. PACKAGE DIMENSIONS

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TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/ LVTTL FREQUENCY SYNTHESIZER

12 REVISION C 11/10/14

Rev Table Page Description of Change Date B Crystal Characteristics Table - added Drive Level. Updated Output Load AC Test Circuit diagrams. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added lead-free marking and note. 2/17/06 Updated Datasheet format. 11/10/14

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