840002-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 14

Technical content

Features

  • Two LVCMOS/LVTTL outputs@ 3.3V, 17 typical output impedance
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended TEST_CLK
  • Output frequency range: 56MHz to 175MHz
  • VCO range: 560MHz to 700MHz
  • Output skew: 12ps (maximum)
  • RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz): 0.47ps (typical) Phase Noise: Offset Noise Power
  • Full 3.3V or mixed 3.3V core/2.5V output supply modes
  • -30°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Frequency Select Function Table Inputs Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 F_SEL1 GND GND VDDO XTAL_IN XTAL_OUTVDD VDDA nPLL_SEL MR OE TEST_CLK nXTAL_SEL F_SEL0 Block Diagram Pin Assignment OSC Phase Detector VCO M = ÷25 (fixed) F_SEL1:0 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 ÷5 N OE F_SEL1:0 nPLL_SEL nXTAL_SEL XTAL_IN XTAL_OUT TEST_CLK MR Pullup Pullup:Pullup Pulldown Pulldown Pulldown Pulldown 840002-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 3 TEST_CLK Input Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels.

4 OE Input Pullup

Output enable. When logic HIGH, the outputs are active. When LOW, the outputs are in high-impedance state. LVCMOS/LVTTL interface levels.

5 MR Input Pulldown

frequency/N output divider. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 8V DD Power Core supply pin. 11 V DDO Power Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. 16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.

Rev E 11/12/14 3 FEMTOCLOCK®, CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5%, TA = -30°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5%, TA = -30°C to 85°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 5m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE, F_SEL0, F_SEL1 V DD = VIN = 3.465V or 2.625V 5 µA MR, TEST_CLK, nXTAL_SEL, nPLL_SEL VDD = VIN =3.465V or 2.625V 150 µA IIL Input Low Current OE, F_SEL0, F_SEL1 VDD = 3.465V or 2.625V, VIN = 0V -150 µA MR, TEST_CLK, nXTAL_SEL, nPLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V±5% 2.6 V VDDO = 2.5V±5% 1.8 V VOL Output Low Voltage; NOTE 1 V DDO = 3.3V±5% or 2.5V±5% 0.5 V

Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to Phase Noise Plot. For NOTES, see Table 5A above.

Rev E 11/12/14 5 FEMTOCLOCK®, CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET Typical Phase Noise at 62.5MHz (3.3V) Typical Phase Noise at 156.25MHz (3.3V) 1Gb Ethernet Filter Phase Noise Result by adding a 1Gb Ethernet filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) Offset Frequency (Hz) Noise Power dBc Hz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Offset Frequency (Hz) Noise Power dBc Hz

Rev E 11/12/14 6 FEMTOCLOCK®, CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET Parameter Measurement Information 3.3V Core/3.3V Output Load AC Test Circuit RMS Phase Jitter Output Skew 3.3V Core/2.5V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDA, VDDO Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF Q[0:1] SCOPE Qx LVCMOS VDDO GND VDD, VDDA VDDO 2.05V±5% -1.25V±5% 1.25V±5% tsk(o) VDDO VDDO Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:1]

Rev E 11/12/14 7 FEMTOCLOCK®, CRYST AL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET Applications Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached.

Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP

Rev E 11/12/14 11 FEMTOCLOCK®, CR YSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET

Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Rev E 11/12/14 12 FEMTOCLOCK®, CR YSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B Features Section - corrected the integration range from 1.875MHz - 175MHz to 1.875MHz - 20MHz in the RMS phase jitter bullet. Crystal Characteristics Table - added Drive Level. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added Lead-Free part number, marking and note. 1/13/06 C T5A T5B 3.3V AC Characteristics Table - added thermal note. 3.3V/2.5V AC Characteristics Table -corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max. Deleted Power Supply Filtering Techniques section, added to schematic layout. Deleted Crystal Input Interface section. Added Overdriving the XTAL Interface section. Updated Layout Guideline and diagram. Ordering Information Table - deleted “ICS” prefix in Part/Order Number column. Converted datasheet format. 2/3/11 D T5B AC Characteristics Table - updated odc to include spec at 125MHz. Ordering Information Table - corrected Package column to replace LQFP with TSSOP. 2/29/12 D 5A, 5B 4 AC Table; f OUT = F_SEL[1:0] = 01 or 11, F_SEL[1:0] = 10 9/28/12 D 8 11 Deleted Quantity from Tape and Reel E T8 11 Removed leaded devices - PDN CQ-13-02 expired. Updated Data Sheet format. 11/12/14

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