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FemtoClock® LVCMOS/LVTTL Clock Generator 840001I-25 Data Sheet ©2016 Integrated Device Technology, Inc Revision A January 15, 20161 GENERAL DESCRIPTION The 840001I-25 is a General Purpose Clock Generator and a member of the family of high performance devices from IDT. The 840001I-25 can accept frequency from a 22.4MHz to 170MHz and generate a 22.4MHz to 170MHz output. The 840001I-25 has excellent phase jitter performance, from 637kHz – 10MHz integration range. The 840001I-25 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.

FEATURES

  • One LVCMOS/LVTTL output, 15Ω output impedence
  • Output frequency range: 22.4MHz – 170MHz
  • VCO range: 560MHz to 680MHz
  • RMS phase jitter @ 125MHz (637kHz - 10MHz): 0.36ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 840001I-25 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VDD REF_IN SEL_0 SEL_1 Q VDDO GND SEL_2 BLOCK DIAGRAM P IN ASSIGNMENT COMMONLY USED FREQUENCY TABLE Inputs Output Frequency (MHz) SEL2 SEL1 SEL0 M Divider N Divider REF_IN (MHz) Q 000 2 5 2 5 2 5 2 5 0 0 1 10 25 62.5 25 0 1 0 4 25 156.25 25 0 1 1 5 25 125 25 1 0 0 10 10 62.5 62.5 1 0 1 5 5 125 125 1 1 0 4 4 156.25 156.25 1 1 1 10 25 62.5 25 (default) Phase Detector VCO 560-680MHz M ÷4, ÷5, ÷10, ÷25 ÷10 ÷25 Pullup PullupREF_IN SEL_[0:2] Q N

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 2 REF_IN Input Pullup Reference input frequency. LVCMOS/LVTTL interface levels. 3, 4, 5 SEL_0, SEL_1, SEL_2 Input Pullup M and N confi guration select pins. LVCMOS/LVTTL interface levels. 6 GND Power Power supply ground. 8 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision A January 15, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 129.5°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, V DD = V DDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 83 mA I DDO Output Supply Current No Load 2 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 80 mA I DDO Output Supply Current No Load 2 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO =2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.465V 2 V DD + 0.3 V V DD = 2.625V 1.7 V DD + 0.3 V V IL Input Low Voltage V DD V DD I IH Input High Current REF_IN, SEL_[0:2] V DD = V IN = 3.465V or 2.625V 5 µA I IL Input Low Current REF_IN, SEL_[0:2] V DD = 3.465V or 2.625V, V IN = 0V -150 µA V OH Output High Voltage; NOTE 1 V DDO = 3.465V 2.6 V V DDO = 2.625V 1.8 V V OL Output Low Voltage; NOTE 1 V DDO = 3.465V or 2.625V 0.6 V NOTE 1: Outputs terminated with 50Ω to V DDO /2. See Parameter Measurement Information Section, “Output Load Test Circuit” diagrams.

©2016 Integrated Device Technology, Inc Revision A January 15, 20164 TABLE 4A. AC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 22.4 170 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 125MHz, Integration Range: 637kHz - 10MHz 0.37 ps 156.25MHz, Integration Range: 637kHz - 10MHz 0.38 ps t R / t F Output Rise/Fall Time 20% to 80% 150 650 ps odc Output Duty Cycle 47 53 % NOTE 1: Please refer to the Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 22.4 170 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 125MHz, Integration Range: 637kHz - 10MHz 0.36 ps 156.25MHz, Integration Range: 637kHz - 10MHz 0.35 ps t R / t F Output Rise/Fall Time 20% to 80% 150 650 ps odc Output Duty Cycle 47 53 % NOTE 1: Please refer to the Phase Noise Plot. TABLE 4B. AC CHARACTERISTICS, V DD = V DDO

©2016 Integrated Device Technology, Inc Revision A January 15, 20165 TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.37ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Filter OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V NOISE POWER dBc Hz 156.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.38ps (typical) ➤ Filter Raw Phase Noise Data ➤Raw Phase Noise Data Phase Noise Result by adding a Filter to raw data ➤Phase Noise Result by adding a Filter to raw data

©2016 Integrated Device Technology, Inc Revision A January 15, 20166 PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT 20% 80% 80% 20% tR tF 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Q

©2016 Integrated Device Technology, Inc Revision A January 15, 20167

APPLICATION INFORMATION

INPUTS: LVCMOS CONTROL PINS: All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT PINS

©2016 Integrated Device Technology, Inc Revision A January 15, 20168 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 840001I-25. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 840001I-25 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation

  • Power (core, output) = V DD_MAX * (I DD + I DDO LVCMOS Output Power Dissipation
  • Output Impedance R OUT Power Dissipation due to Loading 50Ω to V DDO Output Current I OUT = V DDO_MAX / [2 * (50Ω + R OUT
  • Power Dissipation on the R OUT per LVCMOS output Power (R OUT ) = R OUT * (I OUT = 15Ω * (26.6mA) = 10.6mW per output
  • Dynamic Power Dissipation at 156.25MHz Power (156.25MHz) = C PD * Frequency * (V DDO = 6pF * 156.25MHz * (3.465V) = 11.26mW per output Total Power Dissipation
  • Total Power = Power (core, output) + Power Dissipation (R OUT ) + Dyamic Power Dissipation (156.25MHz) = 294.5mW + 10.6mW + 11.26mW = 316.4mW

TABLE 5. THERMAL RESISTANCE θJA FOR 8-LEAD TSSOP, FORCED CONVECTION moderate air fl ow of 1meter per second and a multi-layer board, the appropriate value is 125.5°C/W per Table 5. type of board (multi-layer).

TABLE 6. θ

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A January 15, 201612 REVISION HISTORY SHEET Rev Table Page Description of Change Date Updated data sheet format. 7/29/15 AT 8 General Description - removed Hiperclocks. Ordering Information - removed Lead Free note below the table. Updated header and footer. 1/15/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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