DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 15
Technical content
Features
- Two LVCMOS/LVTTL outputs, 22 typical output impedance One main clock output (Q) One three-state reference clock output (REF_OUT)
- Crystal oscillator interface can accept crystals from 15.3125MHz to 42.67MHz, 18pF parallel resonant crystal
- Q output frequency range: 81.67MHz to 213.33MHz
- RMS phase jitter @106.25, (637kHz – 10MHz): 0.38ps (typical)
- VCO range: 490MHz to 640MHz
- Full 3.3V and 2.5V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Common Application Configuration Table Block Diagram Inputs Output Frequency (MHz) ApplicationCrystal (MHz) M Divider VCO (MHz) N Divider 40 15 600 6 100 (default) Serial Attached (SCSI), PCI Express, Processor Clock 26.5625 24 637.5 6 106.25 Fibre Channel 40 15 600 4 150 Serial ATA (SATA), Processor Clock 26.5625 24 637.5 3 212.5 Fibre Channel 2 25 25 625 5 125 Ethernet 25 25 625 4 156.25 10 Gigabit Ethernet 22.5 25 562.5 3 187.5 12 Gigabit Ethernet 19.44 32 622.08 4 155.52 SONET OSC Phase Detector VCO 490MHz - 640MHz N-Div 00 = ÷3 01 = ÷4 10 = ÷5 11 = ÷6 (default) M-Div 11 = ÷15 (default) 10 = ÷24 01 = ÷25 00 = ÷32 REF_OUT Q OE XTAL_IN XTAL_OUT (Pullup) (Pullup) (Pullup) (Pullup) (Pullup)N0 5 6 7 8 16 15 14 13 OE XTAL_IN XTAL_OUT Q VDDO GND VDD nc nc nc REF_OUT VDDA Pin Assignment 840001-34
16 Lead VFQFN
3mm x 3mm x 0.925 package body K Package Top View Femtoclocks™ Crystal-to-LVCMOS/LVTTL Frequency Synthesizer 840001I-34 Data Sheet
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics forces REF_OUT to Hi-Z state. See Table 3A. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 4, 5 M0, M1 Input Pullup M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B. 6, 14, 15 nc Unused No connect. 7, 8 No, N1 Input Pullup Determines output divider value as defined in Table 3C. LVCMOS/LVTTL interface levels. 9V DD Power Core supply pin. 10 GND Power Power supply ground. DDO Power Output supply pin. 12 Q Output Single-ended clock output. 22 typical output impedance. LVCMOS/LVTTL interface levels. 13 REF_OUT Output Single-ended three-state reference clock output. 22 typical output impedance. LVCMOS/LVTTL interface levels. 16 V DDA Power Analog supply pin.
3©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Table 3A. Control Input Function Table Table 3B. M Divider Function Table Table 3C. N Divider Function Table Control Input Output OE REF_OUT
0 Hi-Z
1 Active (default)
Feedback Divider RatioM1 M0 00 ÷ 3 2 01 ÷ 2 5 10 ÷ 2 4 1 1 ÷15 (default) Control Inputs Output Divider RatioN1 N0 00 ÷ 3 01 ÷ 4 10 ÷ 5 1 1 ÷6 (default)
4©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 76.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 35 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 90 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 25 mA
Table 5. Crystal Characteristics NOTE: It is not recommended to overdrive the crystal input with an external clock.
6©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85° NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Please refer to Phase Noise Plot. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 81.67 213.33 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 100MHz, Integration Range: 637kHz – 10MHz 0.54 ps 106.25MHz, Integration Range: 637kHz – 10MHz 0.38 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle Q, N = 3 40 60 % Q, N 34 8 5 2 % REF_OUT 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 81.67 213.33 MHz tjit(Ø) RMS Phase Jitter, Random; NOTE 1 100MHz, Integration Range: 637kHz – 10MHz 0.54 ps 106.25MHz, Integration Range: 637kHz – 10MHz 0.38 ps tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle Q, N = 3 35 65 % Q, N 34 0 6 0 % REF_OUT 45 55 %
7©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Typical Phase Noise at 100MHz (3.3V) Typical Phase Noise at 106.25MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 100MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.54ps (typical) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.38ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)
8©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Parameter Measurement Information 3.3V LVCMOS Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVCMOS Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period SCOPE Qx GND VDDA VDD, VDDO 1.65V±5% 1.65V±5% -1.65V±5% Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF Q, REF_OUT SCOPE Qx GND VDDA VDD, VDDO 1.25V±5% 1.25V±5% -1.25V±5% REF_OUT tPERIOD tPW tPERIOD odc = VDDO x 100% tPW
of pad pattern for the leads to avoid any shorts. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
Table 8. Package Dimensions
13©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet
Ordering Information
Table 9. Ordering Information
14©2016 Integrated Device Technology, Inc Revision A January 15, 2016 840001I-34 Data Sheet Revision History Sheet Rev Table Page Description of Change Date A Updated VFQFN EPAD Thermal Release Path section. Updated Package Drawing. Ordering Information Table - corrected Temperature column. 10/27/08 A T5 Deleted HiPerClockS references. Crystal Characteristics Table - added note. Deleted application note, LVCMOS to XTAL Interface. Deleted quantity from tape and reel. Deleted Lead-Free note. 10/16/12 A Removed ICS from the part number where needed. Updated data sheet header and footer. 1/15/16
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com 840001I-34 Data Sheet