SN54ALS112A TI | Alldatasheet

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SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 Copyright  1994, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) ′ALS112A 50 6

description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LXXXL H L LXXX H † H † H H ↓ LL Q 0 Q 0 H H ↓ HLH L H H ↓ LHL H H H ↓ H H Toggle H H H X X Q 0 Q 0 † The output levels in this configuration may not meet the minimum levels for VOH . Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. SN54ALS112A ...J PACKAGE SN74ALS112A ...D O R N PACKAGE (TOP VIEW) SN54ALS112A . . . FK PACKAGE (TOP VIEW) NC – No internal connection 1CLK 1PRE GND VCC 1CLR 2CLR 2CLK 2PRE 321 2 0 1 9 91 0 1 1 1 2 1 3 2CLR 2CLK NC 1PRE NC 1CLK 2Q V 1CLR CC GND NC 2PRE NC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol† S R 1PRE 1CLR 1CLK 2PRE 2CLR 2CLK † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) PRE CLK K Q Q CLR J absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions SN54ALS112A SN74ALS112A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –0.4 –0.4 mA IOL Low-level output current 4 8 mA fclock Clock frequency 0 25 0 30 MHz PRE or CLR low 15 10 tw Pulse duration CLK high 20 16.5 ns CLK low 20 16.5 t Set p time before CLK↓ Data 25 22 nstsu Setup time before CLK ↓ PRE or CLR inactive 22 20 ns th Hold time after CLK↓ Data 0 0 ns TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS112A SN74ALS112A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VOH VCC = 4.5 V to 5.5 V,IOH = –0.4 mA VCC –2 VCC –2 V VOL VCC =45V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL VCC = 4.5 V IOL = 8 mA 0.35 0.5 V II J, K, or CLK VCC =55V VI=7V 0.1 0.1 mAII PRE or CLR VCC = 5.5 V, VI = 7 V 0.2 0.2 mA IIH J, K, or CLK VCC =55V VI=27V 20 20 µAIIH PRE or CLR VCC = 5.5 V, VI = 2.7 V 40 40 µA IIL J, K, or CLK VCC =55V VI=04V –0.2 –0.2 mAIIL PRE or CLR VCC = 5.5 V, VI = 0.4 V –0.4 –0.4 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.

SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics (see Figure 1) PARAMETER FROM (INPUT ) TO (OUTPUT ) VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω , TA = MIN to MAX† UNIT(INPUT) (OUTPUT) SN54ALS112A SN74ALS112A MIN MAX MIN MAX fmax 25 30 MHz tPLH PRE or CLR Qo rQ 3 26 3 15 ns tPHL PRE or CLR Q or Q 4 23 4 18 ns tPLH CLK Qo rQ 3 23 3 15 ns tPHL CLK Q or Q 5 24 5 19 ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms

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