SN54ALS109A TI | Alldatasheet
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SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 Copyright 1995, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) ′ALS109A 50 6 ′AS109A 129 29
description
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LXXXL H L LXXX H † H † H H ↑ LLL H H H ↑ H L Toggle H H ↑ LH Q 0 Q 0 H H ↑ HHH L H H L X X Q0 Q 0 † The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near V IL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. SN54ALS109A, SN54AS109A ...J PACKAGE SN74ALS109A, SN74AS109A ...D O R N PACKAGE (TOP VIEW) SN54ALS109A, SN54AS109A . . . FK PACKAGE (TOP VIEW) NC – No internal connection 1CLR 1CLK 1PRE GND VCC 2CLR 2CLK 2PRE 2Q321 2 0 1 9 91 0 1 1 1 2 1 3 NC 2CLK 2PRE 1CLK NC 1PRE 1CLR NC V 2CLR GND NC CC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995
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logic symbol† S 1CLK 2CLK 1PRE 2PRE 1CLR R 2CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS109A SN74ALS109A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –0.4 –0.4 mA IOL Low-level output current 4 8 mA fclock Clock frequency 0 30 0 34 MHz PRE or CLR low 15 15 tw Pulse duration CLK high 16.5 14.5 ns CLK low 16.5 14.5 t Set p time before CLK↑ Data 15 15 nstsu Setup time before CLK ↑ PRE or CLR inactive 10 10 ns th Hold time after CLK↑ Data 0 0 ns TA Operating free-air temperature –55 125 0 70 °C
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54ALS109A SN74ALS109A UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V VOL VCC =45V IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL VCC = 4.5 V IOL = 8 mA 0.35 0.5 V II CLK, J, or K VCC =55V VI=7V 0.1 0.1 mAII PRE or CLR VCC = 5.5 V, VI = 7 V 0.2 0.2 mA IIH CLK, J, or K VCC =55V VI=27V 20 20 µAIIH PRE or CLR VCC = 5.5 V, VI = 2.7 V 40 40 µA IIL CLK, J, or K VCC =55V VI=04V –0.2 –0.2 mAIIL PRE or CLR VCC = 5.5 V, VI = 0.4 V –0.4 –0.4 mA IO ‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded. switching characteristics (see Figure 1) PARAMETER FROM (INPU T) TO (OU TP U T) VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω , TA = MIN to MAX§ UNIT(INPUT) (OUTPUT) SN54ALS109A SN74ALS109A MIN MAX MIN MAX fmax 30 34 MHz tPLH PRE or CLR Qo rQ 3 17 3 13 ns tPHL PRE or CLR Q or Q 5 17 5 15 ns tPLH CLK Qo rQ 5 21 5 16 ns tPHL CLK Q or Q 5 20 5 18 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS109A SN74AS109A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –2 –2 mA IOL Low-level output current 20 20 mA fclock* Clock frequency 0 90 0 105 MHz PRE or CLR low 4 4 tw * Pulse duration CLK high 4 4 ns CLK low 5.5 5.5 t * Set p time before CLK↑ Data 5.5 5.5 nstsu* Setup time before CLK ↑ PRE or CLR inactive 2 2 ns th* Hold time after CLK↑ Data 0 0 ns TA Operating free-air temperature –55 125 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54AS109A SN74AS109A UNITPARAMETER TEST CONDITIONS MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VOH VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2 V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH CLK, J, or K VCC =55V VI=27V 20 20 µAIIH PRE or CLR VCC = 5.5 V, VI = 2.7 V 40 40 µA IIL CLK, J, or K VCC =55V VI=04V –0.5 –0.5 mAIIL PRE or CLR VCC = 5.5 V, VI = 0.4 V –1.8 –1.8 mA IO § VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA ICC VCC = 5.5 V, See Note 1 11.5 17 11.5 17 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS . NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics (see Figure 1) PARAMETER FROM (INPU T) TO (OU TP U T) VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω , TA = MIN to MAX† UNIT(INPUT) (OUTPUT) SN54AS109A SN74AS109A MIN MAX MIN MAX fmax * 90 105 MHz tPLH PRE or CLR Qo rQ 2 9 2 8 ns tPHL PRE or CLR Q or Q 3.5 11.5 3.5 10.5 ns tPLH CLK Qo rQ 2.5 10 2.5 9 ns tPHL CLK Q or Q 3.5 10.5 3.5 9 ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 84000012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8400001EA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC 8400001FA OBSOLETE CFP W 16 None Call TI Call TI JM38510/37102B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/37102BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN54ALS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN54AS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN74ALS109AD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ALS109ADR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ALS109AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS109AN3 OBSOLETE PDIP N 16 None Call TI Call TI SN74ALS109ANSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109AD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109ADR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74AS109ANSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SNJ54ALS109AFK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54ALS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SNJ54AS109AFK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54AS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2
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