83PR226I-01

83PR226I-01_17 IDT | Alldatasheet

Document overview

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• PDF pages: 22

Technical content

Features

• Footprint compatible with 5mm x 7mm differential oscillators
• One differential LVPECL output pair
• Crystal oscillator interface which can also be overdriven a single-ended or differential reference clock
• Output frequency range: 83.33MHz – 213.33MHz
• Crystal/Input frequency range: 15.625MHz – 32MHz
• VCO range: 500MHz – 640MHz
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• Cycle-to-cycle jitter: 45ps (maximum)
• RMS phase jitter @ 125MHz, 1.875MHz – 20MHz: 0.47ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages Common Applications and Settings (not exhaustive) M1 M0 N1 N0 XTAL (MHz) Output Freq (MHz) Application(s) 0 0 1 0 19.44 155.52 SONET 0 0 1 0 19.2 153.6 W-CDMA 0 0 1 1 19.2 122.8 W-CDMA 0 1 0 0 26.5625 106.25 1G, 2G Fibre Channel 0 1 0 1 26.5625 212.5 2G, 4G Fibre Channel 1 0 0 1 25 166.66 Processor, PCI-X 1 1 0 0 24 100 Processor, PCI Express 1 1 1 0 1 24 200 Processor, PCI Express 2 1 1 0 1 22.5 187.5 12G Ethernet 1 1 1 0 25 156.25 10 Gb Ethernet 1 1 1 1 25 125 1 Gb Ethernet (default) Pin Assignments VEE XTAL_IN XTAL_OUT 10 9 nQ VCC Q 83PR226I-01 10-VFQFN 5mm x 7mm x 1mm package body K Package Top View 83PR226I-01 Datasheet Programmable FemtoClock ® LVPECL Oscillator Replacement

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics values: ÷32, ÷25, ÷24, or ÷20 (see Table 3A). LVCMOS/LVTTL interface levels. 3V EE Power Negative supply pin. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. ÷3, ÷4, ÷5, or ÷6 (see Table 3B). LVCMOS/LVTTL interface levels.

3©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Function Tables Table 3A. Feedback Divider M Function Table Table 3B. Output Divider N Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C, Tb = 105°C M1 M0 M Value 00 ÷ 32 01 ÷ 24 10 ÷ 20 11 ÷ 25 N1 N0 M Value 00 ÷ 6 01 ÷ 3 10 ÷ 4 11 ÷ 5 Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 38.05C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 172 mA

NOTE 1: Outputs termination with 50 to VCC – 2V. NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics

5©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C, Tb = 105°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Please refer to the Phase Noise plots. NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 4: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 5: This parameter is guaranteed using a 25MHz crystal. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 83.33 213.33 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 45 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.44 ps 125MHz, Integration Range: 1.875MHz – 20MHz 0.47 ps 100MHz, Integration Range: 1.875MHz – 20MHz 0.48 ps tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 3 100MHz, (1.2MHz – 21.9MHz), 106 samples, 25MHz crystal input 17.20 ps 125MHz, (1.2MHz – 21.9MHz), 106 samples, 25MHz crystal input 16.52 ps tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 4 100MHz, 25MHz crystal input 1.70 ps 125MHz, 25MHz crystal input 1.61 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 % tLOCK PLL Lock Time; NOTE 5 100 ms

6©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C, Tb = 105°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Please refer to the Phase Noise plots. NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 4: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 5: This parameter is guaranteed using a 25MHz crystal. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 83.33 213.33 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 45 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 156.25MHz, Integration Range: 1.875MHz – 20MHz 0.44 ps 125MHz, Integration Range: 1.875MHz – 20MHz 0.48 ps 100MHz, Integration Range: 1.875MHz – 20MHz 0.49 ps tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 3 100MHz, (1.2MHz – 21.9MHz), 106 samples, 25MHz crystal input 12.18 ps 125MHz, (1.2MHz – 21.9MHz), 106 samples, 25MHz crystal input 16.41 ps tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 4 100MHz, 25MHz crystal input 1.47 ps 125MHz, 25MHz crystal input 1.74 ps tR / tF Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 47 53 % tLOCK PLL Lock Time; NOTE 5 100 ms

7©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 100MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

8©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Typical Phase Noise at 125MHz (3.3V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

9©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period RMS Phase Jitter SCOPE Qx nQx VEE VCC -1.3V ± 0.165V tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q nQ Q SCOPE Qx nQx VEE VCC -0.5V ± 0.125V nQ Q Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power

10©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Parameter Measurement Information, continued PLL Lock Time Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be ad ded for additional protection. A 1k  resistor can be used. Lock Time Not to Scale VCC VEE Supply Voltage Output 95% of VCC Correct Frequency

on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to a void any shorts. and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat s lug and the land patt ern. Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology . Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

16©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) SerDes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)  H3(s)  [H1(s) – H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g. for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in RMS. The two evaluation ranges for PCI Express Gen 2 are: 10kHz – 1.5MHz (Low Band), and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

This section provides information on power dissipation and junction temperature for the 83PR226I-01. Equations and example calculations are also provided. The total power dissipation for the 83PR226I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX  IEE_MAX = 3.465V  172mA = 595.98mW
• Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 595.98mW + 30mW = 625.98mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA  Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 38.05°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board.

Table 7. Thermal Resistance JA for 10-VFQFN, Forced Convection

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX ) = 0.9V
• For logic low, VOUT = VOL_MAX = VCO_MAX – 1.7V (VCC_MAX – VOL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL]  (VCC_MAX – VOH_MAX ) = [(2V – (VCC_MAX – VOH_MAX ))/RL]  (VCC_MAX – VOH_MAX ) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL]  (VCC_MAX – VOL_MAX ) = [(2V – (VCC_MAX – VOL_MAX ))/RL]  (VCC_MAX – VOL_MAX ) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW VOUT VCC VCC - 2V RL 50Ω

Table 8. JA vs. Air Flow Table for a 10-VFQFN Table 9. JB for a 10-VFQFN

20©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Package Outline Package Outline - K Suffix for 10-Lead VFQFN

21©2017 Integrated Device Technology, Inc. October 6, 2017 83PR226I-01 Datasheet Package Outline - K Suffix for 10-VFQFN (CONT)

22©2017 Integrated Device Technology, Inc. October 6, 2017 DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantability, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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Ordering Information

Table 10. Ordering Information October 6, 2017 Added the Tb = 105°C test condition to all DC and AC electrical characteristics tables. Replaced ICS package drawing with IDT drawing. Updated data sheet header/footer. Ordering Information - removed quantity from tape and reel. Deleted LF note below table. Removed ICS from part numbers where needed. Updated data sheet header and footer. August 10, 2010 AC Characteristics Tables - added NOTE 5 to PLL Lock Time. AC Characteristics Tables - added PLL Lock Time spec. Added thermal note and updated PCIe notes. Added PLL Lock Time Diagram. Updated Overdriving the XTAL Interface section. Added PCIe Application Note. July 31, 2008 Package Dimensions - added 0.1mm dimension to small pad.