83PN187I IDT | Alldatasheet

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Technical content

Features

  • Fourth Generation FemtoClock® Next Generation (NG) technology
  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVPECL output pair
  • Crystal oscillator interface can also be overdriven by a single-ended reference clock
  • Output frequency range: 125MHz –187.5MHz
  • Crystal/input frequency: 25MHz, 12pF parallel resonant crystal
  • VCO range: 2GHz – 2.5GHz
  • Cycle-to-cycle jitter: 10ps (maximum), 3.3V±5%
  • RMS phase jitter @ 156.25MHz, 12kHz – 20MHz: 0.339ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Common Applications and Settings FSEL[1:0] XTAL (MHz) Output Fr equency (MHz) A pplication(s) 00 25 156.25 XAUI, 10GigE 01 25 187.5 8Gig Fibre Channel 10 25 125 Ethernet 11 (default) 25 150 SAS, Embedded Processor Control Logic Pullup Pullup Pullup Q nQ OSC PFD FemtoClock® NG VCO XTAL_IN XTAL_OUT FSEL0 FSEL1 OE Pin Assignment 83PN187I 10-Lead VFQFN 5mm x 7mm x 1mm package body K Package Top View Block Diagram VCC nQ Q RESERVED OE XTAL_IN XTAL_OUT FSEL0 FSEL1 910 VEE 83PN187I Data Sheet Programmable FemtoClock® NG LVPECL Oscillator Replacement

Table 1. Pin Descriptions Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Divider Function Table 1 OE Input Pullup Output enable. LV CMOS/LVTTL interface levels. 2 RESERVED Reserve Reserved pin. Do not connect. 3V EE Power Negative supply pin. oscillator interface can also be driven by a single-ended reference clock. 6, 7 Q, nQ Output Differen tial output pair. LVPECL interface levels. 8V CC Power Power supply pin. 9 FSEL0 Input Pullup Output divider control inputs. Sets the output divider value to one of four values. See Table 3. LVCMOS/LVTTL interface levels. 10 FSEL1 Input Pullup Output divider control inputs. Sets the output divider value to one of four values.

3©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 39.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 131 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 124 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics

5©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Table 6A. AC Characteristics, Vcc = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Table 6B. AC Characteristics, Vcc = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 1250 187.5 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 156.25MHz, Integration Range: 12kHz – 20MHz 0.339 0.5 ps 187.5MHz, Integration Range: 12kHz – 20MHz 0.321 0.5 ps 125MHz, Integration Range: 12kHz – 20MHz 0.309 0.5 ps 150MHz, Integration Range: 12kHz – 20MHz 0.315 0.5 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 10 ps tR / tF Output Rise/Fall Time 20% to 80% 100 350 ps odc Output Duty Cycle 49 51 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 125 187.5 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 156.25MHz, Integration Range: 12kHz – 20MHz 0.347 0.5 ps 187.5MHz, Integration Range: 12kHz – 20MHz 0.326 0.5 ps 125MHz, Integration Range: 12kHz – 20MHz 0.315 0.5 ps 150MHz, Integration Range: 12kHz – 20MHz 0.317 0.5 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 20 ps tR / tF Output Rise/Fall Time 20% to 80% 100 350 ps odc Output Duty Cycle 49 51 %

6©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Typical Phase Noise at 125MHz (3.3V core, 3.3V output) Typical Phase Noise at 150MHz (3.3V core, 3.3V output) Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz

7©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Typical Phase Noise at 156.25MHz (3.3V core, 3.3V output) Typical Phase Noise at 187.5MHz (3.3V core, 3.3V output) Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz

8©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter SCOPE Qx nQx VEE VCC -1.3V ± 0.165V nQ Q SCOPE Qx nQx VEE VCC -0.5V ± 0.125V nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q

9©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet

Application Information

Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k  resistor can be used. VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 1. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

11©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 83PN187I. Equations and example calculations are also provided. The total power dissipation for the 83PN187I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below. Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection

Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN

16©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Package Outline Package Outline - K Suffix for 10-Lead VFQFN ccc C PLANE SEATING 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch Page 1 O f 4 PAC KAG E O UTLINE MLP Q UAD 0.08 C A B C bbb C A B INDEX AREA (D/ 2 xE/ 2) (D/ 2 xE/ 2) INDEX AREA aaa C 2x TO P VIEW9 aaa C 2x SIDE VIEW BO TTO M VIEW PIN# 1 ID FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 D E NX b1 NX b2 bbb C A B A NX L1 NX L2

17©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Package Outline, continued Package Outline - K Suffix for 10-Lead VFQFN PAG E: 2 of 4 aaa 0.1 5 bbb 0.1 0 ccc 0.1 0 TO LERANC E O F FO RM AND PO SITIO N C O MMO N DIMENSIO N 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 Size Body 5.00X7.00 Pit ch (e1 & e2) 1 .00/ 2.54 Lead C ount 1 0 Lead Summar y Table Var iat ion VNJR- 1 Ver y Ver y Thin R0.30 Pin # 1 ID NO MMIN MAX 1 .00 0.05 1 , 2NO TES A 1 , 2 0.00 0.80 1 , 2 0.02 0.90 C O MMO N DIMENSIO N SYMBO L V : Ver y t hin

18©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Package Outline, continued Package Outline - K Suffix for 10-Lead VFQFN PAG E: 3 of 4 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD NO TE: 1 . Dimensioning and t oler ancing conf or m t o ASME Y1 4.5M- 1 994. 2. All dimensions ar e in millimet er s, angles ar e in degr ees(°). 3. N is t he t ot al number of t er minals. 4. The locat ion of t he t er minal # 1 ident if ier and ter minal number ing convent ion conf or ms t o JEDEC publicat ion 95 SPP- 002. 5. ND and NE r ef er t o t he number of t er minals on each D and E side r espect ively. 6. NJR r ef er s t o NO N JEDEC REG ISTERED 7. Dimension b applies t o met allized t er minal and is measur ed bet ween 0.1 0mm and 0.30mm f r om t he t er minal t ip. If t he t er minal has t he opt ional r adius on t he ot her end of t he t er minal, t he dimension b should not be measur ed in t hat r adius ar ea. 8. C oplanar it y applies t o t he t er minals and all ot her bot t om sur f ace met allizat ion. 9. Dr awing shown ar e f or illust r at ion only. FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8

19©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Package Outline, continued Package Outline - K Suffix for 10-Lead VFQFN 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD PAG E: 4 of 4 PAD DESIG N NE NO TES N ND 1 0 Symbol Var iat ion 0.65 0.55 0.45 3.80 3.70 3.55 1 .80 1 .70 1 .55 MIN NO ML1 MAX NO M MIN MAX E BSC MIN NO M MAX Not e MIN NO M MAX 0.45 0.40 0.35 5.00 7.00 D BSC FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 VNJR- 1 1 .40NO M MAX 1 .45 MIN 1 .35 1 .1 0NO ML2 MAX 1 .20 MIN 1 .00

20©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet

Ordering Information

Table 9. Ordering Information

21©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN187I Data Sheet Revision History Sheet Rev Table Page Description of Change Date Updated 10-Lead VFQFN package information. 6/02/11 A Removed ICS from part numbers where needed. Updated header and footer. 3/4/16

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