83PN156I IDT | Alldatasheet

Document overview

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Technical content

Features

  • Fourth Generation FemtoClock® Next Generation (NG) technology
  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVPECL output pair
  • Crystal oscillator interface which can also be overdriven using a single-ended reference clock
  • Output frequency range: 100MHz –156.25MHz
  • Crystal/input frequency range: 20MHz – 25MHz, parallel resonant crystal
  • VCO range: 2GHz – 2.5GHz
  • RMS phase jitter @ 156.25MHz, 12kHz – 20MHz: 0.348ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Common Applications and Settings FSEL1:FSEL0 XTAL (MHz) Output Frequency (MHz) Application(s) 00 25 100 PCI Express 01 25 125 Ethernet 10 25 150 SAS, Embedded Processor 11 (default) 25 156.25 10 Gigabit Ethernet XAUI, Rocket IO (default) VCC nQ Q RESERVED OE XTAL_IN XTAL_OUT FSEL0 FSEL1 910 VEE Pullup Pullup Pullup Q nQ OSC PFD FemtoClock® NG VCO XTAL_IN XTAL_OUT FSEL0 FSEL1 OE Control Logic Pin Assignment 83PN156I 10-Lead VFQFN 5mm x 7mm x 1mm package body K Package Top View Block Diagram 83PN156I Data Sheet Programmable FemtoClock® NG LVPECL Oscillator Replacement

Table 1. Pin Descriptions Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Divider Function Table 1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels. 2 RESERVED Reserve Reserved pin. Do not connect. 3V EE Power Negative supply pin. oscillator interface which can also be overdriven using a single-ended reference clock. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. Table 3. LVCMOS/LVTTL interface levels. Table 3. LVCMOS/LVTTL interface levels

3©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 39.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 131 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 124 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics

5©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Table 6A. AC Characteristics, Vcc = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF resonant crystal. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Table 6B. AC Characteristics, Vcc = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF resonant crystal. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units fMAX Output Frequency 100 156.25 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 156.25MHz, Integration Range: 12kHz – 20MHz 0.348 0.5 ps 150MHz, Integration Range: 12kHz – 20MHz 0.318 0.5 ps 125MHz, Integration Range: 12kHz – 20MHz 0.314 0.5 ps 100MHz, Integration Range: 12kHz – 20MHz 0.323 0.5 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 10 ps tR / tF Output Rise/Fall Time 20% to 80% 100 350 ps odc Output Duty Cycle 49 51 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 100 156.25 MHz tjit(Ø) RMS Phase Jitter (Random) 156.25MHz, Integration Range: 12kHz – 20MHz 0.353 0.5 ps 150MHz, Integration Range: 12kHz – 20MHz 0.322 0.5 ps 125MHz, Integration Range: 12kHz – 20MHz 0.319 0.5 ps 100MHz, Integration Range: 12kHz – 20MHz 0.326 0.5 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 15 ps tR / tF Output Rise/Fall Time 20% to 80% 100 350 ps odc Output Duty Cycle 49 51 %

6©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Typical Phase Noise at 100MHz @ 3.3V Offset Frequency (Hz) Noise Power dBc Hz

7©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Typical Phase Noise at 156.25MHz @ 3.3V Offset Frequency (Hz) Noise Power dBc Hz

8©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Q nQ LVPECL VEE VCC -1.3V±0.165V nQ Q SCOPE Q nQ LVPECL VEE VCC -0.5V±0.125V tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q nQ Q

11©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k  resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 83PN156I. Equations and example calculations are also provided. The total power dissipation for the 83PN156I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below. Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection

Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN Table 9. Package Dimensions for 10-Lead VFQFN

16©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Package Outline Package Outline - K Suffix for 10-Lead VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9. ccc C PLANE SEATING 0.08 C C INDEX AREA (D/2 xE/2) aaa C 2x TOP VIEW9 aaa C 2x SIDE VIEW BOTTOM VIEW PIN#1 ID E bbb C A B A NX L1 ccc C PLANE SEATING 0.08 C A B C bbb C A B INDEX AREA (D/2 xE/2) (D/2 xE/2) INDEX AREA aaa C 2x TOP VIEW9 aaa C 2x SIDE VIEW BOTTOM VIEW PIN#1 ID D E NX b1 NX b2 bbb C A B A NX L1 NX L2 0.1mm→ → 0.1mm N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1)

17©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet

Ordering Information

Table 10. Ordering Information

18©2016 Integrated Device Technology, Inc Revision A March 4, 2016 83PN156I Data Sheet Revision History Sheet Rev Table Page Description of Change Date A 3 Absolute Maximum Ratings - corrected supply voltage to 3.63V. Updated Overdriving the XTAL Interface application note. 4/25/11 A Removed ICS from part number where needed. Updated header and footer. 3/4/16

DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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