DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 21

Technical content

Features

  • Fourth Generation FemtoClock® NG technology
  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVPECL output pair
  • Crystal oscillator interface which can also be overdriven using a single-ended reference clock
  • Output frequency: 100MHz - 156.25390625MHz
  • Crystal/input frequency: 25MHz, 12pF parallel resonant crystal
  • VCO range: 2GHz – 2.5GHz
  • RMS phase jitter @ 156.25MHz, 10kHz – 1MHz: 0.179ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging Common Applications and Settings Block Diagram FSEL1, FSEL0 XTAL (MHz) Output Frequency (MHz) Application(s) 00 25 100 PCI Express 01 25 125 Ethernet 10 25 150 SAS, Embedded Processor 11 (default) 25 156.25 10 Gi gabit Ethernet (default) 11 (default) 25.000625 156.25390625 10 GbE, Frequency Margining (+25ppm) Pullup Pullup Pullup Control Logic OSC FemtoClock® NG VCO 2 - 2.5GHz OE XTAL_IN 25MHz XTAL_OUT FSEL0 FSEL1 PFD LPF Q nQ VCC nQ Q RESERVED OE XTAL_IN XTAL_OUT FSEL0 FSEL1 910 VEE Pin Assignment 83PN15639 10-Lead VFQFN 5mm x 7mm x 1mm package body Top View 83PN15639 Datasheet Programmable FemtoClock® NG 3.3V, 2.5V LVPECL Oscillator Replacement

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels. 2 RESERVED Reserve Reserved pin. Do not connect. EE Power Negative supply pin. XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. values. LVCMOS/LVTTL interface levels. values. LVCMOS/LVTTL interface levels.

3©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 36.8C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 140 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 117 135 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

NOTE 1: Outputs termination with 50 to VCC – 2V. Table 5. Crystal Characteristics

25 MHz

25.000625 MHz

Table 6. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF resonant crystal. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

6©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Q nQ LVPECL VEE VCC -1.3V±0.165V nQ Q SCOPE Q nQ LVPECL VEE VCC -0.5V±0.125V tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q nQ Q

the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. Leadframe Base Package, Amkor Technology. Figure 1. P .C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

This section provides information on power dissipation and junction temperature for the 83PN15639. Equations and example calculations are also provided. The total power dissipation for the 83PN15639 is the sum of the core power plus the power dissipation due to the load. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation due to th e load.

  • Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
  • Power (outputs) MAX = 32mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 32mW = 517.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 36.8°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.517W * 36.8°C/W = 104°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 10-Lead VFQFN, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V.

  • For logic high, V OUT = VOH_MAX = VCC_MAX – 0.8V (VCC_MAX – VOH_MAX) = 0.8V
  • For logic low, V OUT = VOL_MAX = VCC_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW VOUT VCC VCC - 2V RL 50Ω

Table 8. JA vs. Air Flow Table for a 10-Lead VFQFN

15©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline ccc C PLANE SEATING 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch Page 1 Of 4 PACKAGE OUTLINE MLP QUAD 0.08 C A B C bbb C A B INDEX AREA (D/2 xE/2) (D/2 xE/2) INDEX AREA aaa C 2x TOP VIEW9 aaa C 2x SIDE VIEW BOTTOM VIEW PIN#1 ID FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ENGINEERING MANAGER DATE TOOLING MANAGER TECH. SALES MANAGER ORIGINATOR DWG. NO : PKGML00305 DRAFT ZAHRUL ARAVEN KANDA 2007-APR-18 D E 3.70 NX b1 NX b2 bbb C A B A NX L1 NX L2 6.25

16©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued PAGE: 2 of 4 aaa 0.15 bbb 0.10 ccc 0.10 TOLERANCE OF FORM AND POSITION COMMON DIMENSION 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PACKAGE OUTLINE MLP QUAD FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ENGINEERING MANAGER DATE TOOLING MANAGER TECH. SALES MANAGER ORIGINATOR DWG. NO : PKGML00305 DRAFT ZAHRUL ARAVEN KANDA 2007-APR-18 Size Body 5.00X7.00 Pitch (e1 & e2) 1.00/2.54 Lead Count Lead Summary Table Variation VNJR-1 Very Very Thin R0.30 Pin #1 ID NOMMIN MAX 1.00 0.05 1, 2NOTES A 1, 2 0.00 0.80 1, 2 0.02 0.90 COMMON DIMENSION SYMBOL V : Very thin

17©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued PAGE: 3 of 4 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PACKAGE OUTLINE MLP QUAD NOTE: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angles are in degrees(°). 3. N is the total number of terminals. 4. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SPP-002. 5. ND and NE refer to the number of terminals on each D and E side respectively. 6. NJR refers to NON JEDEC REGISTERED 7. Dimension b applies to metallized terminal and is measured between 0.10mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 8. Coplanarity applies to the terminals and all other bottom surface metallization. 9. Drawing shown are for illustration only. FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ENGINEERING MANAGER DATE TOOLING MANAGER TECH. SALES MANAGER ORIGINATOR DWG. NO : PKGML00305 DRAFT ZAHRUL ARAVEN KANDA 2007-APR-18

18©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet 10-Lead VFQFN, NR Suffix Package Outline, continued 5.00x7.00 MLPQ 10LD 1.00/2.54 Pitch PACKAGE OUTLINE MLP QUAD PAGE: 4 of 4 PAD DESIGN NE NOTES N ND Symbol Variation 0.65 0.55 0.45 3.80 3.70 3.55 1.80 1.70 1.55 MIN NOML1 MAX NOM MIN MAX E BSC MIN NOM MAX Note MIN NOM MAX 0.45 0.40 0.35 5.00 7.00 D BSC FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES. ENGINEERING MANAGER DATE TOOLING MANAGER TECH. SALES MANAGER ORIGINATOR DWG. NO : PKGML00305 DRAFT ZAHRUL ARAVEN KANDA 2007-APR-18 VNJR-1 1.40NOM MAX 1.45 MIN 1.35 1.10NOML2 MAX 1.20 MIN 1.00

19©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet

Ordering Information

Table 9. Ordering Information

20©2016 Integrated Device Technology, Inc. Revision B August 16, 2016 83PN15639 Datasheet Revision History] Revision Date Description of Change August 16, 2016 ▪ Added package dimensions to package outline.

DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com 21©2016 Integrated Device Technology, Inc August 16, 2016