83C528

80C528 PHILIPS | Alldatasheet

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CMOS single-chip 8-bit microcontroller Product specification 1995 Feb 02 INTEGRATED CIRCUITS IC20 Data Handbook

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

21995 Feb 02

DESCRIPTION

The 8XC528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC528 has the same instruction set as the 80C51. Three versions of the derivative exist:

• 83C528 — 32k bytes mask programmable ROM
• 80C528 — ROMless version of the 83C528
• 87C528 — 32k bytes EPROM (described in a separate data sheet) This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. The 8XC528 contains a 32k × 8 ROM (83C528), a 512 × 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a watchdog timer with a separate oscillator, a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 8XC528 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.

FEATURES

• 80C51 instruction set – 32k × 8 ROM (83C528) – ROMless (80C528) – 512 × 8 RAM – Memory addressing capability 64k ROM and 64k RAM – Three 16-bit counter/timers – On-chip watchdog timer with oscillator – Full duplex UART – I2C serial interface – Four 8-bit I/O ports
• Power control modes: – Idle mode – Power-down mode – Warm start from power-down
• CMOS and TTL compatible
• Extended temperature ranges
• ROM code protection
• 7-source and 7-vector interrupt structure with 2 priority levels
• Up to 3 external interrupt request inputs
• Two programmable power reduction modes (Idle and Power-down)
• Termination of Idle mode by any interrupt, external or WDT (watchdog) reset
• XTAL frequency range: 1.2 MHz to 16 MHz PIN CONFIGURATIONS 20 21 40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 SDA/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD DUAL IN-LINE PACKAGE QUAD FLAT PACK 44 34 12 22 LEADED CHIP CARRIER 6 1 40 18 28 20 23 42T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 SDA/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD SHRINK DUAL IN-LINE PACKAGE 21 22VSS P2.0/A8 NC* NC* * DO NOT CONNECT

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 3

CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 18 28 PLCC Pin Function Pin Function

1 NC* 23 NC*

2 P1.0/T2 24 P2.0/A8 3 P1.1/T2EX 25 P2.1/A9 4 P1.2 26 P2.2/A10 5 P1.3 27 P2.3/A11 6 P1.4 28 P2.4/A12 7 P1.5 29 P2.5/A13 8 P1.6/SCL 30 P2.6/A14 9 P1.7/SDA 31 P2.7/A15

10 RST 32 PSEN

11 P3.0/RxD 33 ALE

12 NC* 34 NC*

13 P3.1/TxD 35 EA 14 P3.2/INT0 36 P0.7/AD7 15 P3.3/INT1 37 P0.6/AD6 16 P3.4/T0 38 P0.5/AD5 17 P3.5/T1 39 P0.4/AD4 18 P3.6/WR 40 P0.3/AD3 19 P3.7/RD 41 P0.2/AD2 20 XTAL2 42 P0.1/AD1 21 XTAL1 43 P0.0/AD0

22 VSS 44 V DD

• DO NOT CONNECT PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 12 22 PQFP Pin Function Pin Function 1 P1.5 23 P2.5/A13 2 P1.6/SCL 24 P2.6/A14 3 P1.7/SDA 25 P2.7/A15

4 RST 26 PSEN

5 P3.0/RxD 27 ALE

6 NC* 28 NC*

7 P3.1/TxD 29 EA 8 P3.2/INT0 30 P0.7/AD7 9 P3.3/INT1 31 P0.6/AD6 10 P3.4/T0 32 P0.5/AD5 11 P3.5/T1 33 P0.4/AD4 12 P3.6/WR 34 P0.3/AD3 13 P3.7RD 35 P0.2/AD2 14 XTAL2 36 P0.1/AD1 15 XTAL1 37 P0.0/AD0

16 VSS 38 V DD

17 NC* 39 NC*

18 P2.0/A8 40 P1.0/T2 19 P2.1/A9 41 P1.1/T2EX 20 P2.2/A10 42 P1.2 21 P2.3/A11 43 P1.3 22 P2.4/A12 44 P1.4 * DO NOT CONNECT LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS T2EX RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA PSEN ALE VSSVDD XTAL1 XTAL2 SCL SDA

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 4

ORDERING INFORMATION

ROMless ROM ROMless ROM Drawing Number TEMPERATURE oC RANGE AND PACKAGE FREQ MHz P80C528FBP P83C528FBP/xxx P80C528FBP N P83C528FBP N SOT129-1 0 to +70, Plastic Dual In-line Package16 P80C528FBA P83C528FBA/xxx P80C528FBA A P83C528FBA A SOT187-2 0 to +70, Plastic Leaded Chip Carrier16 P80C528FBB P83C528FBB/xxx P80C528FBB B P83C528FBB B SOT307-2 0 to +70, Plastic Quad Flat Pack 16 P80C528FFP P83C528FFP/xxx P80C528FFP N P83C528FFP N SOT129-1 –40 to +85, Plastic Dual In-line Package16 P80C528FFA P83C528FFA/xxx P80C528FFA A P83C528FFA A SOT187-2 –40 to +85, Plastic Leaded Chip Carrier16 P80C528FFB P83C528FFB/xxx P80C528FFB B P83C528FFB B SOT307-2 –40 to +85, Plastic Quad Flat Pack 16 P80C528FHP P83C528FHP/xxx P80C528FHP N P83C528FHP N SOT129-1 –40 to +125, Plastic Dual In-line Package16 P80C528FHA P83C528FHA/xxx P80C528FHA A P83C528FHA A SOT187-2 –40 to +125, Plastic Leaded Chip Carrier16 P80C528FHB P83C528FHB/xxx P80C528FHB B P83C528FHB B SOT307-2 –40 to +125, Plastic Quad Flat Pack 16 P83C528FBR/xxx SOT270-1 0 to +70, Plastic Shrink Dual In-Linr Package16 NOTE: 1. xxx denotes the ROM code number.

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 5

P87C528EBP N SOT129-1 0 to +70, Plastic Dual In-line Package16 P87C528EBF FA 0590B 0 to +70, Ceramic Dual In-line Package w/Window 16 P87C528EBA AA SOT187-2 0 to +70, Plastic Leaded Chip Carrier16 P87C528EBL KA 1472A 0 to +70, Ceramic Leaded Chip Carrier w/Window 16 P87C528EBB B SOT307-2 0 to +70, Plastic Quad Flat Pack 16 P87C528EFP N SOT129-1 –40 to +85, Plastic Dual In-line Package16 P87C528EFF FA 0590B –40 to +85, Ceramic Dual In-line Package w/Window 16 P87C528EFF FA SOT187-2 –40 to +85, Plastic Leaded Chip Carrier16 P87C528EFL KA 1472A –40 to +85, Ceramic Leaded Chip Carrier w/Window 16 P87C528EFB B SOT307-2 –40 to +85, Plastic Quad Flat Pack 16 P87C528GBP N SOT129-1 0 to +70, Plastic Dual In-line Package20 P87C528GBF FA 0590B 0 to +70, Ceramic Dual In-line Package w/Window 20 P87C528GBA A SOT187-2 0 to +70, Plastic Leaded Chip Carrier20 P87C528GBL KA 1472A 0 to +70, Ceramic Leaded Chip Carrier w/Window 20 P87C528GFP N SOT129-1 –40 to +85, Plastic Dual In-line Package20 P87C528GFF FA 0590B –40 to +85, Ceramic Dual In-line Package w/Window 20 P87C528GFA A SOT187-2 –40 to +85, Plastic Leaded Chip Carrier20 P87C528GFL KA 1472A –40 to +85, Ceramic Leaded Chip Carrier w/Window 20

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 6

INT0 INT1 CONTROL SERIAL IN SERIAL OUT OSCILLATOR AND TIMING PROGRAM MEMORY (32K x 8 ROM) RAM AUX–RAM DATA MEMORY (256 x 8) TWO 16-BIT TIMER/EVENT COUNTERS DATA MEMORY (256 x 8) 16-BIT TIMER / EVENT COUNTER WATCHDOG TIMER 64K-BYTE BUS EXPANSION CONTROL PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT BIT-LEVEL I2C INTERFACE FREQUENCY REFERENCE T2 T2EX RST EXTERNAL INTERRUPTS PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SHARED WITH PORT 3 INTERNAL INTERRUPTS SDA SCL

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 7

PIN NO. MNEMONIC DIP SDIL LCC QFP TYPE NAME AND FUNCTION VSS 20 21 22 16 I Ground: circuit ground potential. VDD 40 42 44 38 I Power Supply: +5V power supply pin during normal operation, Idle mode and Power-down mode. P0.0–0.7 39–32 41–34 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. 1 1 2 40 I T2 (P1.0): Timer/counter 2 external count input (following edge triggered). 2 2 3 41 I T2EX (P1.1): Timer/counter 2 trigger input. 7 7 8 2 I/O SCL (P1.6): I2C serial port clock line. 8 8 9 3 I/O SDA (P1.7): I2C serial port data line. P2.0–P2.7 21–28 22–29 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 10–17 10–18 (11=NC) 11, 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: 10 10 11 5 I RxD (P3.0): Serial input port 11 12 13 7 O TxD (P3.1): Serial output port 12 13 14 8 I INT0 (P3.2): External interrupt 13 14 15 9 I INT1 (P3.3): External interrupt 14 15 16 10 I T0 (P3.4): Timer 0 external input 15 16 17 11 I T1 (P3.5): Timer 1 external input 16 17 18 12 O WR (P3.6): External data memory write strobe 17 18 19 13 O RD (P3.7): External data memory read strobe RST 9 9 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD . After a watchdog timer overflow, this pin is pulled high while the internal reset signal is active. ALE 30 31 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 30 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 33 35 29 I External Access Enable: EA must be externally held low during RESET to enable the device to fetch code from external program memory locations 0000H to 7FFFH. If EA is held high during RESET, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. EA is don’t care after RESET . XTAL1 19 20 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 19 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

1995 Feb 02 8

Table 1. 8XC524/8XC528 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1995 Feb 02 9

Table 2. Internal and External Program Memory Access with Security Bit Set restrictions for the MOVC instructions. be addressed each in a different way. with R0 and R1 as address pointer. the 8052AH. Timer 2 is a 16-bit timer/counter. low by, for example, an external reset circuit. the RESET signal, WDCON contains A5H. independently of the XTAL-clock. pins have an open drain output configuration.

1995 Feb 02 10

– guarding the I2C status if RBF or WBF = 0. priority registers are IE and IP . Table 3. Description of IE Bits 0 = NO interrupt is enabled. 1 = ANY individually enabled interrupt will be accepted. Table 4. Description of IP Bits

1995 Feb 02 11

oscillator, as shown in the Logic Symbol. the data sheet must be observed. power-down is the last instruction executed. port pin or to external memory. low current operating modes. Table 5. External Pin Status During Idle and Power-Down Modes

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 12

ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70, or –40 to +85, or –40 to +125°C Storage temperature range –65 to +150 °C Voltage on any other pin to VSS –0.5 to VDD +0.5 V Input, output current on any two pins ±10 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±20%), –40°C to +85°C (VDD = 5V ±20%), or –40°C to +125°C (VDD = 5V ±10%), VSS =0V TEST LIMITS SYMBOL PARAMETER PART TYPE CONDITIONS MIN MAX UNIT VIL Input low voltage, except EA, P1.6/SCL, P1.7/SDA 0°C to 70°C –40°C to +85°C –40°C to +125°C –0.5 –0.5 –0.5 0.2VDD –0.1 0.2VDD –0.15 0.2VDD –0.25 V V V VIL1 Input low voltage to EA 0°C to 70°C –40°C to +85°C –40°C to +125°C –0.5 –0.5 –0.5 0.2VDD –0.3 0.2VDD –0.35 0.2VDD –0.45 V V V VIL2 Input low voltage to P1.6/SCL, P1.7/SDA3 –0.5 0.3VDD V VIH Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0°C to 70°C –40°C to +85°C –40°C to +125°C 0.2VDD +0.9 0.2VDD +1.0 0.2VDD +1.0 VDD +0.5 VDD +0.5 VDD +0.5 V V V VIH1 Input high voltage, XTAL1, RST 0°C to 70°C –40°C to +85°C –40°C to +125°C 0.7VDD 0.7VDD +0.1 0.7VDD +0.1 VDD +0.5 VDD +0.5 VDD +0.5 V V V VIH2 Input high voltage, P1.6/SCL, P1.7/SDA3 0.7VDD 6.0 V VOL Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA1 IOL = 1.6mA4 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN1 IOL = 3.2mA4 0.45 V VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA4 0.4 V VOH Output high voltage, ports 1, 2, 3 VDD = 5V ±10%, IOH = –60µA 2.4 V IOH = –25µA 0.75VDD V IOH = –10µA 0.9VDD V VOH1 Output high voltage, Port 0 in external bus mode, ALE, PSEN , RST2 VDD = 5V ±10%, IOH = –800µA IOH = –300µA 2.4 0.75VDD V V IOH = –80µA 0.9VDD V IIL Logical 0 input current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA 0°C to 70°C –40°C to +85°C –40°C to +125°C VIN = 0.45V –50 –75 –75 µA µA µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA 0°C to 70°C –40°C to +85°C –40°C to +125°C See note 5 –650 –750 –750 µA µA µA

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 13

DC ELECTRICAL CHARACTERISTICS (Continued) Tamb = 0°C to +70°C (VDD = 5V ±20%), –40°C to +85°C (VDD = 5V ±20%), or –40°C to +125°C (VDD = 5V ±10%), VSS =0V TEST LIMITS SYMBOL PARAMETER PART TYPE CONDITIONS MIN MAX UNIT IIL1 Input leakage current, port 0, EA 0.45<Vi<VDD ±10 µA IIL2 Input leakage current, P1.6/SCL, P1.7/SDA 0V<Vi<6.0V 0V<V DD <6.0V ±10 µA µA IDD Power supply current: See notes 6, 7 Active mode 35 mA Idle mode 6 mA Power down mode Power down mode –40°C to +125°C 100 150 µA µA R RST Internal reset pull-down resistor 50 150 kΩ C IO Capacitance of I/O buffer Freq.=1MHz Tamb = 25°C 10 pF NOTES: 1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level ouput voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0 transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 3. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so a voltage below 0.3VDD will be recognized as a logic 0 while an input above 0.7VDD will be recognized as a logic 1. 4. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10mA Maximum IOL per 8–bit port: – Port 0: 26mA Ports 1, 2, & 3: 15mA Maximum total IOL for all output pins: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 5. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. See Figures 9 through 12 for IDD test conditions. 7. IDDMAX at other frequencies can be derived from the figure below, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA. MAX ACTIVE MODE TYP ACTIVE MODE MAX IDLE MODE TYP IDLE MODE I IDD vs. FREQUENCY DD (mA) FREQ. AT XTAL1 (MHz) 4 8 12 16 VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF DEVICE UNDER TEST.

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 14

AC ELECTRICAL CHARACTERISTICS 1, 2 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 1 Oscillator frequency 1.2 16 MHz tLHLL 1 ALE pulse width 85 2tCLCL –40 ns tAVLL 1 Address valid to ALE low 8 tCLCL –55 ns tLLAX 1 Address hold after ALE low 28 tCLCL –35 ns tLLIV 1 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 1 ALE low to PSEN low 23 tCLCL –40 ns tPLPH 1 PSEN pulse width 143 3tCLCL –45 ns tPLIV 1 PSEN low to valid instruction in 83 3tCLCL –105 ns tPXIX 1 Input instruction hold after PSEN 0 0 ns tPXIZ 1 Input instruction float after PSEN 38 tCLCL –25 ns tAVIV 1 Address to valid instruction in 208 5tCLCL –105 ns tPLAZ 1 PSEN low to address float 10 10 ns Data Memory tRLRH 2, 3 RD pulse width 275 6tCLCL –100 ns tWLWH 2, 3 WR pulse width 275 6tCLCL –100 ns tRLDV 2, 3 RD low to valid data in 148 5tCLCL –165 ns tRHDX 2, 3 Data hold after RD 0 0 ns tRHDZ 2, 3 Data float after RD 55 2tCLCL –70 ns tLLDV 2, 3 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 2, 3 Address to valid data in 398 9tCLCL –165 ns tLLWL 2, 3 ALE low to RD or WR low 138 238 3tCLCL –50 3tCLCL +50 ns tAVWL 2, 3 Address valid to WR low or RD low 120 4tCLCL –130 ns tQVWX 2, 3 Data valid to WR transition 3 tCLCL –60 ns tWHQX 2, 3 Data hold after WR 13 tCLCL –50 ns tRLAZ 2, 3 RD low to address float 0 0 ns tWHLH 2, 3 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 6 High time 20 20 ns tCLCX 6 Low time 20 20 ns tCLCH 6 Rise time 20 20 ns tCHCL 6 Fall time 20 20 ns Shift Register tXLXL 4 Serial port clock cycle time 750 12tCLCL ns tQVXH 4 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 4 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 4 Input data hold after clock rising edge 0 0 ns tXHDV 4 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 15

AC ELECTRICAL CHARACTERISTICS – I 2C INTERFACE SYMBOL PARAMETER INPUT OUTPUT I2C SPECIFICATION SCL TIMING CHARACTERISTICS tHD;STA START condition hold time ≥ 14 tCLCL 1 Note 2 ≥ 4.0µs tLOW SCL LOW time ≥ 16 tCLCL Note 2 ≥ 4.7µs tHIGH SCL HIGH time ≥ 14 tCLCL 1 ≥ 80 tCLCL 3 ≥ 4.0µs tRC SCL rise time ≤ 1µs4 Note 5 ≤ 1.0µs tFC SCL fall time ≤ 0.3µs4 ≤ 0.3µs 6 ≤ 0.3µs SDA TIMING CHARACTERISTICS tSU;DAT1 Data set-up time ≥ 250ns Note 2 ≥ 250ns tHD;DAT Data hold time ≥ 0ns Note 2 ≥ 0ns tSU;STA Repeated START set-up time ≥ 14 tCLCL 1 Note 2 ≥ 4.7µs tSU;STO STOP condition set-up time ≥ 14 tCLCL 1 Note 2 ≥ 4.0µs tBUF Bus free time ≥ 14 tCLCL 1 Note 2 ≥ 4.7µs tRD SDA rise time ≤ 1µs4 Note 5 ≤ 1.0µs tFD SDA fall time ≤ 0.3µs4 ≤ 0.3µs 6 ≤ 0.3µs NOTES: 2. This parameter is determined by the user software, it has to comply with the I2C. 3. This value gives the autoclock pulse length which meets the I2C specification for the specified XTAL clock frequency range. Alternatively, the SCL pulse may be timed by software. 4. Spikes on SDA and SCL lines with a duration of less than 4 × fCLK will be filtered out. 5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs. 6. The maximum capacitance on bus lines SDA and SCL is 400pF.

1995 Feb 02 16

Figure 1. External Program Memory Read Cycle Figure 2. External Data Memory Read Cycle

1995 Feb 02 17

Figure 3. External Data Memory Write Cycle Figure 4. Shift Register Mode Timing Figure 5. Timing SIO1 (I2C) Interface

0.7 VDD

0.3 VDD

1995 Feb 02 18

Figure 6. External Clock Drive Figure 7. AC Testing Input/Output Figure 8. Float Waveform AC inputs during testing are driven at VDD –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ’1’ and VIL for a logic ’0’. VOL level occurs. IOH /IOL ≥ ± 20mA.

1995 Feb 02 19

Figure 9. IDD Test Condition, Active Mode Figure 10. IDD Test Condition, Idle Mode Figure 11. Clock Signal Waveform for Figure 12. IDD Test Condition, Power Down Mode exceed the IOL1 specifications.

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 20

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 21

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 22

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 23

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 24

0590B 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE) NOTES: 1. Controlling dimension: Inches. Millimeters are 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. “T”, “D”, and “E” are reference datums on the body 4. These dimensions measured with the leads 5. Pin numbers start with Pin #1 and continue 6. Denotes window location for EPROM products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane T. counterclockwise to Pin #40 when viewed shown in parentheses. from the top. – D – PIN # 1 – E – 0.225 (5.72) MAX. 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) – T – SEATING PLANE 0.620 (15.75) 0.590 (14.99) (NOTE 4) 0.598 (15.19) 0.571 (14.50) BSC 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (NOTE 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) BSC 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) SEE NOTE 6 853–0590B 06688

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 25

1472A 44-PIN CERQUAD J-BEND (K) PACKAGE NOTES: 1. All dimensions and tolerances to conform 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only. 1.02 (0.040) X 45° 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) CHAMFER 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) on each side. to ANSI Y14.5–1982. 2 3 3 X 0.63 (0.025) R MIN. 3.05 (0.120) 2.29 (0.090) 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.38 (0.015) 0.51 (0.02) X 45° 17.65 (0.656) 17.40 (0.685) 1.27 (0.050) 12.7 (0.500) 8.13 (0.320) 7.37 (0.290) 40X 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.15 (0.006) MIN. 0.15 (0.006) 90 + 5 –10 ° ° 0.076 (0.003) MIN. DETAIL B mm/(inch) SEE DET AIL B SEE DET AIL A DETAIL A TYP. ALL SIDES mm/(inch) 1.52 (0.060) REF. SEATING PLANE 1.02 + 0.25 (0.040 + 0.010) BASE PLANE 45 TYP.

4 PLACES

1.27 (0.050) TYP. NOMINAL 8.13 (0.320) 7.37 (0.290) 853-1472A 05854

Philips Semiconductors Product specification 80C528/83C528CMOS single-chip 8-bit microcontrollers

1995 Feb 02 26

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.