83C451

80C451 PHILIPS | Alldatasheet

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Technical content

/C0109 /C0110 /C0114 80C451/83C451/87C451 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook

1998 May 01

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

21998 May 01 853-0830 19327

DESCRIPTION

The Philips 8XC451 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC451 (includes the 80C451, 87C451 and 83C451) is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines for a total of 68 pins. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 8XC451 includes a 4k × 8 ROM (83C451) EPROM (87C451), a 128 × 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 80C451 ROMless version includes all of the 83C451 features except the on-board 4k × 8 ROM. The 87C451 has 4k of EPROM on-chip as program memory and is otherwise identical to the 83C451. The 8XC451 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.

FEATURES

• 80C51 based architecture
• Seven 8-bit I/O ports
• Port 6 features: – Eight data pins – Four control pins – Direct MPU bus interface – Parallel printer interface
• On the microcontroller: – 4k × 8 ROM (83C451) 4k × 8 EPROM (87C451) ROMless version (80C451) – 128 × 8 RAM – Two 16-bit counter/timers – Two external interrupts
• External memory addressing capability – 64k ROM and 64k RAM
• Low power consumption: – Normal operation: less than 24mA at 5V, 12MHz – Idle mode – Power-down mode PIN CONFIGURATION LCC 916 1 27 43 Pin Function 1E A /VPP 2 P2.0/A8 3 P2.1/A9 4 P2.2/A10 5 P2.3/A11 6 P2.4/A12 7 P2.5/A13 8 P2.6/A14 9 P2.7/A15 10 P0.7/AD7 11 P0.6/AD6 12 P0.5/AD5 13 P0.4/AD4 14 P0.3/AD3 15 P0.2/AD2 16 P0.1/AD1 17 P0.0/AD0 18 V CC 19 P4.7 20 P4.6 21 P4.5 22 P4.4 23 P4.3 Pin Function 24 P4.2 25 P4.1 26 P4.0 27 P1.0 28 P1.1 29 P1.2 30 P1.3 31 P1.4 32 P1.5 33 P1.6 34 P1.7

35 RST

36 P3.0/RxD 37 P3.1/TxD 38 P3.2/INT0 39 P3.3/INT1 40 P3.4/T0 41 P3.5/T1 42 P3.6/WR 43 P3.7/RD 44 P5.0 45 P5.1 46 P5.2 Pin Function 47 P5.3 48 P5.4 49 P5.5 50 P5.6 51 P5.7

52 XTAL2

53 XTAL1

55 ODS

56 IDS

57 BFLAG

58 AFLAG

59 P6.0 60 P6.1 61 P6.2 62 P6.3 63 P6.4 64 P6.5 65 P6.6 66 P6.7

67 PSEN

68 ALE/PROG

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 3

INTERRUPT, SERIAL PORT AND TIMER BLOCKS PORT 4 DRIVERS PORT 4 LATCH P4.0–P4.7 PORT 5 DRIVERS PORT 5 LATCH P5.0–5.7 PORT 6 LATCH PORT 6 DRIVERS P6.0–P6.7 PORT 6 CONTROL/STATUS IDS ODS AFLAG BFLAG 4K x 8 ROM/EPROM SU00086

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 4

ORDERING INFORMATION

TEMPERATURE RANGE °C AND PACKAGE FREQ MHz DRAWING NUMBER SC80C451CCA68 SC83C451CCA68 SC87C451CCA68 OTP 0 to +70, Plastic Leaded Chip Carrier,3.5 to 12 SOT188-3 SC80C451CGA68 SC83C451CGA68 SC87C451CGA68 OTP 0 to +70, Plastic Leaded Chip Carrier3.5 to 16 SOT188-3 NOTE: 1. OTP = One Time Programmable LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA /VPP PSEN ALE/PROG VSSVCC XTAL1 XTAL2PORT 6 PORT 4 PORT 5 PORT 6 CONTROL ODS IDS BFLAG AFLAG SU00085

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 5

NO. TYPE NAME AND FUNCTION VSS 54 I Ground: 0V reference. VCC 18 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 17-10 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. P1.0–P1.7 27-34 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. P2.0–P2.7 2-9 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. P3.0–P3.7 36-43 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: 36 I RxD (P3.0): Serial input port 37 O TxD (P3.1): Serial output port 38 I INT0 (P3.2): External interrupt 39 I INT1 (P3.3): External interrupt 40 I T0 (P3.4): Timer 0 external input 41 I T1 (P3.5): Timer 1 external input 42 O WR (P3.6): External data memory write strobe 43 O RD (P3.7): External data memory read strobe P4.0–P4.7 26-19 I/O Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. P5.0–P5.7 44-51 I/O Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. P6.0–P6.7 59-66 I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS 55 I ODS : Output data strobe IDS 56 I IDS: Input data strobe BFLAG 57 I/O BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG 58 I/O AFLAG: Bidirectional I/O pin with internal pull-ups RST 35 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC . ALE/PROG 68 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. PSEN 67 O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. EA /VPP 1 I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP ) during EPROM programming. XTAL1 53 I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. XTAL2 52 O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 6

The 8XC451 has a total of seven parallel I/O ports. The first four ports, P0 through P3, are identical in function to those present on the 80C51 family. The added ports 4 and 5 are identical in function to port 1; that is, they are standard quasi-bidirectional ports with no alternate functions and the standard output drive characteristics. Port 6 is a specialized 8-bit bidirectional I/O port with internal pullups. Ports 4 and 5 Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Port 4 and 5 are addressed at the special function register addresses shown in Table 1. Port 6 Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 1). This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pullups. The flexibility of this port facilitates high-speed parallel data communications. This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS , IDS, AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table 1. The following four control pins are used in conjunction with port 6: ODS – Output data strobe (Active Low) for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode). ODS is active low for output driver control. the OBF flag can be programmed to be cleared on the negative or positive edge of ODS IDS – Input data strobe (Active Low) for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS is low and latched on the positive transition of IDS, or to latch only on the positive transition of IDS. Correspondingly, the IBF flag is set on the negative or positive transition of IDS. BFLAG – BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS strobe when BFLAG is high. Both features are enabled when BFLAG is low. This feature facilitates the use of the SC8XC451 in bused multiprocessor systems. AFLAG – AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices. Port 6 can be used in a number of different ways to facilitate data communication. It can be used as a processor bus interface, as a standard quasi-bidirectional I/O port, or as a parallel printer port (either polled or interrupt driven). Processor Bus Interface Port 6 allows the use of an 8XC451 as an element on a microprocessor type bus. The host processor could be a general purpose MPU or the data bus of a microcontroller like the 8XC451 itself. Setting up the 8XC451 as a processor bus interface allows single or multiple microcontrollers to be used on a bus as flexible peripheral processing elements. Applications can include: keyboard scanners, serial I/O controllers, servo controllers, etc. On reset, port 6 is programmed correctly (that is, Special Function registers CSR and P6) for use as a bus interface. This prevents the interface from disrupting data on the bus of a host processor during power-up. Standard Quasi-bidirectional I/O Port To use port 6 as a common I/O port, all of the control pins should be tied to ground. On hardware reset, bits 2-7 of the CSR are set to one. With the control pins grounded, the port’s operation and electrical characteristics will be identical to port 1 on the 80C51. No further software initialization is required. Parallel Printer Port The 8XC451 has the capacity to permit all of the intelligent features of a common printer to be handled by a single chip. The features of port 6 allow a parallel port to be designed with only line driving and receiving chips required as additional hardware. The onboard UART allows RS232 interfacing with only level shifting chips added. The 8-bit parallel ports 0 to 6 are ample to drive onboard control functions, even when ports are used for external memory access, interrupts, and other functions. The RAM addressing ability of ports 0 to 2 can be used to address up to 64k bytes of a hardware buffer/spooler. In addition, either end of a parallel interface can be implemented using port 6, and the interfaces can be interrupt driven or polled in either case. For more detailed information on port 6 usage, refer to the application notes entitled “80C451 Operation of Port 6” and “256k Centronics Printer Buffer Using the SC87C451 Microcontroller.” CONTROL STATUS REGISTER The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 3). CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS. This can occur on the negative or positive edge of IDS, as determined by CSR.2 IBF is cleared when the CPU reads the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag is set to a logic 1 when the CPU writes to the port 6 output data buffer. OBF is cleared by the positive or negative edge of ODS, as determined by CSR.3. CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high transition on the IDS pin sets the IBF flag. The Port 6 input buffer is loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low transition on the IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high.

1998 May 01 7

CSR.3 = 1, the positive edge of the ODS input clears the OBF flag. Table 1. Special Function Register Addresses Figure 1. Port 6 Block Diagram

1998 May 01 8

Table 2. 8XC451 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1998 May 01 9

Table 3. Control Status Register (CSR)

• Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

of this specification is not implied.

1. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 10

DC ELECTRICAL CHARACTERISTICS 1 Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451) TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYPICAL 1 MAX UNIT VIL Input low voltage; except EA –0.5 0.2VCC –0.1 V VIL1 Input low voltage to EA 0 0.2VCC –0.3 V VIH Input high voltage; except XTAL1, RST 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage; XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage; ports 1, 2, 3, 4, 5, 6 IOL = 1.6mA2 0.45 V VOL1 Output low voltage; port 0, ALE, PSEN IOL = 3.2mA2 0.45 V VOH Output high voltage; ports 1, 2, 3, 4, 5, 6 IOH = –60µA, 2.4 V IOH = –25µA 0.75VCC V IOH = –10µA 0.9VCC V VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN )3 IOH = –800µA, IOH = –300µA IOH = –80µA 2.4 0.75VCC 0.9VCC V V V IIL Logical 0 input current,; ports 1, 2, 3, 4, 5, 6VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6See note 4 –650 µA ILI Input leakage current; port 0 VIN = VIL or VIH +10 µA ICC Power supply current: See note 6 Active mode @ 12MHz5 11.5 25 mA Idle mode @ 12MHz5 1.3 4 mA Power down mode 3 50 µA R RST Internal reset pull-down resistor 50 300 kΩ C IO Pin capacitance7 10 pF NOTES: 1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 0.94 X FREQ + 13.71 Idle mode: ICCMAX = 0.14 X FREQ +2.31 where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 13. 6. See Figures 14 through 17 for ICC test conditions. 7. CIO applies to ports 1 through 6, AFLAG, BFLAG, XTAL1, XTAL2.

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 11

AC ELECTRICAL CHARACTERISTICS 1 Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)2 12MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency: Speed Versions SC8XC451 C 3.5 12 MHz SC8XC451 G 3.5 16 MHz tLHLL 2 ALE pulse width 127 2tCLCL –40 ns tAVLL 2 Address valid to ALE low 28 tCLCL –55 ns tLLAX 2 Address hold after ALE low 48 tCLCL –35 ns tLLIV 2 ALE low to valid instruction in 234 4tCLCL –100 ns tLLPL 2 ALE low to PSEN low 43 tCLCL –40 ns tPLPH 2 PSEN pulse width 205 3tCLCL –45 ns tPLIV 2 PSEN low to valid instruction in 145 3tCLCL –105 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 59 tCLCL –25 ns tAVIV 2 Address to valid instruction in 312 5tCLCL –105 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tRLRH 3, 4 RD pulse width 400 6tCLCL –100 ns tWLWH 3, 4 WR pulse width 400 6tCLCL –100 ns tRLDV 3, 4 RD low to valid data in 252 5tCLCL –165 ns tRHDX 3, 4 Data hold after RD 0 0 ns tRHDZ 3, 4 Data float after RD 97 2tCLCL –70 ns tLLDV 3, 4 ALE low to valid data in 517 8tCLCL –150 ns tAVDV 3, 4 Address to valid data in 585 9tCLCL –165 ns tLLWL 3, 4 ALE low to RD or WR low 200 300 3tCLCL –50 3tCLCL +50 ns tAVWL 3, 4 Address valid to WR low or RD low 203 4tCLCL –130 ns tQVWX 3, 4 Data valid to WR transition 23 tCLCL –60 ns tWHQX 3, 4 Data hold after WR 33 tCLCL –50 ns tRLAZ 3, 4 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 43 123 tCLCL –40 tCLCL +40 ns Shift Register tXLXL 5 Serial port clock cycle time 1.0 12tCLCL µs tQVXH 5 Output data setup to clock rising edge 700 10tCLCL –133 ns tXHQX 5 Output data hold after clock rising edge50 2tCLCL –117 ns tXHDX 5 Input data hold after clock rising edge 0 0 ns tXHDV 5 Clock rising edge to input data valid 700 10tCLCL –133 ns NOTES: SEE NEXT PAGE

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 12

AC ELECTRICAL CHARACTERISTICS 1 (continued) Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)2 12MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT Port 6 input (input rise and fall times = 5ns) tFLFH 8 PE width 270 3tCLCL +20 ns tILIH 8 IDS width 270 3tCLCL +20 ns tDVIH 8 Data setup to IDS high or PE high 0 0 ns tIHDX 8 Data hold after IDS high or PE high 30 30 ns tIVFV 9 IDS to BFLAG (IBF) delay 130 130 ns Port 6 output tOLOH 6 ODS width 270 3tCLCL +20 ns tFVDV 7 SEL to data out delay 85 85 ns tOLDV 6 ODS to data out delay 80 80 ns tOHDZ 6 ODS to data float delay 35 35 ns tOVFV 6 ODS to AFLAG (OBF) delay 100 100 ns tFLDV 6 PE to data out delay 120 120 ns tOHFH 7 ODS to AFLAG (SEL) delay 100 100 ns External Clock tCHCX 10 High time 20 20 ns tCLCX 10 Low time 20 20 ns tCLCH 10 Rise time 20 20 ns tCHCL 10 Fall time 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

1998 May 01 13

AVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Figure 2. External Program Memory Read Cycle Figure 3. External Data Memory Read Cycle

1998 May 01 14

Figure 4. External Data Memory Write Cycle Figure 5. Shift Register Mode Timing

1998 May 01 15

Figure 6. Port 6 Output Figure 7. Port 6 Select Mode Figure 8. Port 6 Input Figure 9. IBF Flag Output

1998 May 01 16

Figure 10. External Clock Drive AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 11. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 12. Float Waveform VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST. Figure 13. ICC vs. FREQ

1998 May 01 17

Figure 14. ICC Test Condition, Active Mode Figure 15. ICC Test Condition, Idle Mode Figure 16. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 17. ICC Test Condition, Power Down Mode

1998 May 01 18

number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 18. Note that the 87C451 is running with a 4 to 6MHz device is executing internal address and program data transfers. low 25 times as shown in Figure 19. programmed, verification cycles will produce only encrypted data. Figure 20. The other pins are held at the ‘Verify Code Data’ levels encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. Table 4. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5V ±10% during programming and verification.

 Trademark phrase of Intel Corporation.

1998 May 01 19

Figure 18. Programming Configuration

25 PULSES

Figure 19. PROG Waveform

0 ENABLE

Figure 20. Program Verification

1998 May 01 20

• FOR PROGRAMMING VERIFICATION SEE FIGURE 18.

FOR VERIFICATION CONDITIONS SEE FIGURE 20. Figure 21. EPROM Programming and Verification

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 21

PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3

Philips Semiconductors Product specification 80C451/83C451/87C45180C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01 22

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 75003857 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.