DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 13

Technical content

Features

  • Twelve LVCMOS/LVTTL outputs
  • Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
  • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
  • Maximum output frequency: 250MHz
  • Output skew: 350ps (maximum)
  • Part-to-part skew: 1.5ns (maximum)
  • 3.3V core, 3.3V output
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • For drop in replacement part use 83948i-147 83948I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND GND VDDO GND VDDO Q11 VDDO Q10 GND VDDO GND VDDO GND VDDO GND Pin Assignment Block Diagram 83948I Datasheet Low Skew, 1-to-12 Differential-to- LVCMOS/LVTTL Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK_SEL Input Pullup Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels. 2 LVCMOS_CLK Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK Input Pullup Non-inverting differential clock input. 4 nCLK Input Pulldown Inverting differential clock input. 5 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. 6 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. DD Power Positive supply pin. 20, 24, 28, 32 GND Power Power supply ground. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 22, 26, 30 VDDO Power Output supply pins.

0 Selected De-selected

1 De-selected Selected

3©2016 Integrated Device Technology, Inc May 19, 2016 83948I Datasheet Table 3B. Clock Input Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Inputs Outputs Input to Output Mode PolarityCLK_SEL LVCMOS_CLK CLK nCLK Q[0:11] 0 – 0 1 LOW Differential to Single-Ended Non-Inverting 0 – 1 0 HIGH Differential to Single-Ended Non-Inverting 0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting 0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting 0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting 0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting 1 0 – – LOW Single-Ended to Single-Ended Non-Inverting 1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Power Supply Current 55 mA

NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 1B: Measured from VDD/2 or crosspoint of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Setup and Hold times are relative to the rising edge of the input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

5©2016 Integrated Device Technology, Inc May 19, 2016 83948I Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Part-to-Part Skew Output Rise/Fall Time Differential Input Level Output Skew Output Pulse Width SCOPE Qx GND VDD, 1.65V±0.15V -1.65V±0.15V VDDO tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy 0.8V 2V 2V 0.8V tR tF Q0:Q11 VDD GND CLK nCLK V CMR Cross Points V PP tsk(o) VDDO VDDO Qx Qy tPW tPERIOD VDDO VDDO VDDO tPW tPERIOD odc = Q0:Q11

6©2016 Integrated Device Technology, Inc May 19, 2016 83948I Datasheet Parameter Measurement Information, continued Propagation Delay nCLK Q0:Q11 CLK tPD VDDO ➤ ➤ VDD 2LVCMOS_CLK

Table 6. JA vs. Air Flow Table for a 32 Lead LQFP

Table 7. Package Dimensions for 32 Lead LQFP

11©2016 Integrated Device Technology, Inc May 19, 2016 83948I Datasheet

Ordering Information

Table 8. Ordering Information

12©2016 Integrated Device Technology, Inc May 19, 2016 83948I Datasheet Revision History Sheet Rev Table Page Description of Change Date B T5 4 AC Characteristics table - tLZ, tHZ row changed symbol to read t PLZ, tPHZ and changed Parameter to read Output Enable Time. Added rows: tS ""Clock Enable Setup Time"" and tH ""Clock Enable Hold Time"". 5/20/02 B T5 4 AC Characteristics table, t S and tH rows - replaced SYNC_OE with CLK_EN. Added an extra note to Propagation Delay row. 6/26/02 BT 5 4 AC Characteristics table, fMAX row corrected typo error of 150MHz to 250MHz. 8/8/02 B T5 4 AC Characteristics table - tPW row, added f< 150MHz for tPW Test Conditions. 11/11/02 C Features Section - added Lead-Free bullet. Pin Characteristics Table - changed C IN from 4pF max. to 4pF typical. Added Recommendations for Unused Output Pins. Ordering Information Table - added Lead-Free part number, marking and note. 12/15/05 CT 8 Added Differential Clock Input Interface Section. Ordering Information Table - corrected Temperature column. Updated datasheet format. 3/6/08 C T8 11 Removed leaded orderable parts fr om Ordering Information table 11/14/12 C General Description - Removed ICS Chip and HiPerClockS. Features Section - Removed reference to leaded packages Removed ICS from the Part Number. Ordering Information - Removed ICS from the Part/Order Number. Removed 1000 from the Tape & Reel. Removed the LF note from below the table. Updated Header and Footer. 12/16/15 C Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 5/19/16

DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com 83948I Datasheet