83948I-147 Datasheet
Document overview
- Manufacturer or author: Integrated Device Technology
- PDF pages: 17
Technical content
Features
- Twelve LVCMOS/LVTTL outputs
- Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
- CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
- Output frequency: 350MHz
- Additive phase jitter, RMS: 0.14ps (typical)
- Output skew: 100ps (maximum), 3.3V±5%
- Part-to-part skew: 1ns (maximum), 3.3V±5%
- Operating supply modes:
- Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging Block Diagram Pin Assignment 83948I-147 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View D Q Q10 Q11 CLK_EN CLK_SEL OE LVCMOS_CLK CLK nCLK 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND GND VDDO GND VDDO Q11 VDDO Q10 GND VDDO GND VDDO GND VDDO GND 83948I-147 Data Sheet Low Skew, 1-to-1 Differential- to-LVCMOS/ LVTTL Fanout Buffer
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK_SEL Input Pullup Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
2 LVCMOS_CL
K Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. 3 CLK Input Pullup Non-inverting differential clock input. 4 nCLK Input Pulldown Inverting differential clock input. 5 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. 6 OE Input Pullup Output enable pin. When LOW, outputs are in an High-impedance state. when HIGH, outputs are active. LVCMOS/LVTTL interface levels. 20, 24, 28, 32 GND Power Power supply ground. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 22, 26, 30 VDDO Power Output supply pins.
0 CLK/nCLK inputs selected
1 LVCMOS_CLK input selected
3©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Inputs Outputs Input to Output Mode PolarityCLK_SEL LVCMOS_CLK CLK nCLK Q[0:11] 0 – 0 1 LOW Differential to Single-Ended Non-Inverting 0 – 1 0 HIGH Differential to Single-Ended Non-Inverting 0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting 0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting 0 – Biased; NOTE 1 0 HIGH Single-E nded to Single-Ended Inverting 0 – Biased; NOTE 1 1 LOW Single-E nded to Single-Ended Inverting 1 0 – – LOW Single-Ended to Single-Ended Non-Inverting 1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.6C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 55 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 52 mA
4©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Table 4C. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 4D. DC Characteristics, TA = -40°C to 85°C NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, Output Load AC Test Circuit diagrams. NOTE 2: VIL should not be less than -0.3V. NOTE 3: Common mode voltage is defined as VIH. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 55 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS V DD = 3.465V 2 V DD + 0.3 V LVCMOS V DD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage LVCMOS V DD = 3.465V -0.3 0.8 V LVCMOS V DD = 2.625V -0.3 0.7 V IIN Input Current V IN = VDD or VIN = 3.465V or 2.625V 300 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ± 5% IOH = -24mA 2.4 V VDDO = 2.5V ± 5% IOH = -15mA 1.8 V VOL Output Low Voltage; NOTE 1 VDDO = 3.3V ± 5% IOL = 24mA 0.55 V VDDO = 3.3V ± 5% IOL = 12mA 0.30 V VDDO = 2.5V ± 5% IOL = 15mA 0.6 V VPP Peak-to-Peak Input Voltage; NOTE 2 CLK/nCLK V DD = 3.465V or 2.625V 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 2, 3 CLK/nCLK VDD = 3.465V or 2.625V GND + 0.5 V DD – 0.85 V
5©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units f MAX Output Frequency 350 MHz tPD Propagation Delay CLK/nCLK; NOTE 1 ƒ 350MHz 2 4 ns LVCMOS_CLK; NOTE 2 ƒ 350MHz 2 4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.14 1 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge @ VDDO/2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on the Rising Edge @ VDDO/2 1n s tR / tF Output Rise/Fall Time 0.8V to 2V 0.2 1.0 ns odc Output Duty Cycle ƒ 150MHz, Ref = CLK/nCLK 45 50 55 % tPZL, tPZH Output Enable Time; NOTE 5 5n s tPLZ, tPHZ Output Disable Time; NOTE 5 5n s tS Clock Enable Setup Time; NOTE 6 CLK_EN to CLK/nCLK 1 ns CLK_EN to LVCMOS_CLK 0n s tH Clock Enable Hold Time; NOTE 6 CLK/nCLK to CLK_EN 0 ns LVCMOS_CLK to CLK_EN 1n s
6©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to V DDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tPD Propagation Delay CLK/nCLK; NOTE 1 ƒ 350MHz 1.5 4.2 ns LVCMOS_CLK; NOTE 2 ƒ 350MHz 1.7 4.4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.14 1 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge @ VDDO/2 160 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on the Rising Edge @ VDDO/2 2n s tR / tF Output Rise/Fall Time 0.6V to 1.8V 0.1 1.0 ns odc Output Duty Cycle ƒ 150MHz, Ref = CLK/nCLK 40 60 % tPZL, tPZH Output Enable Time; NOTE 5 5n s tPLZ, tPHZ Output Disable Time; NOTE 5 5n s tS Clock Enable Setup Time; NOTE 6 CLK_EN to CLK/nCLK 1 ns CLK_EN to LVCMOS_CLK 0n s t H Clock Enable Hold Time; NOTE 6 CLK/nCLK to CLK_EN 0 ns LVCMOS_CLK to CLK_EN 1n s
7©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to V DDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tPD Propagation Delay CLK/nCLK; NOTE 1 ƒ 350MHz 2 4 ns LVCMOS_CLK; NOTE 2 ƒ 350MHz 2 4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz – 20MHz 0.14 1 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge @ VDDO/2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on the Rising Edge @ VDDO/2 1n s tR / tF Output Rise/Fall Time 0.8V to 2V 0.1 1.0 ns odc Output Duty Cycle ƒ 200MHz, Ref = CLK/nCLK 45 55 % tPZL, tPZH Output Enable Time; NOTE 5 5n s tPLZ, tPHZ Output Disable Time; NOTE 5 5n s tS Clock Enable Setup Time; NOTE 6 CLK_EN to CLK/nCLK 1 ns CLK_EN to LVCMOS_CLK 0n s t H Clock Enable Hold Time; NOTE 6 CLK/nCLK to CLK_EN 0 ns LVCMOS_CLK to CLK_EN 1n s
8©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter, RMS @ 155.52MHz (12kHz to 20MHz) = 0.14ps (typical) SSB Phase Noise dBc/Hz Offset From Carrier Frequency (Hz)
9©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Part-to-Part Skew 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit Differential Input Level Output Skew SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDD -1.25V±5% 1.25V±5% 2.05V±5% VDDO tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO VDD GND CLK nCLK V CMR Cross Points V PP tsk(o) VDDO VDDO Qx Qy
10©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Parameter Measurement Information, continued 3.3V Output Rise/Fall Time Propagation Delay 2.5V Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period 0.8V 2V 2V 0.8V tR tF Q0:Q11 nCLK Q0:Q11 CLK tPD VDDO ➤ ➤ VDD 2CLK 0.6V 1.8V 1.8V 0.6V tR tF Q0:Q11 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q11
Table 6. JA vs. Air Flow Table for a 32-Lead LQFP
Table 7. Package Dimensions for 32-Lead LQFP
15©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet
Ordering Information
Table 8. Ordering Information
16©2016 Integrated Device Technology, Inc Revision D March 30, 2016 83948I-147 Data Sheet Revision History Sheet Rev Table Page Description of Change Date B Features Section - added Lead-Free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical; and added 5 min. and 12 max to ROUT. Updated Single Ended Signal Driving Differential Input diagram. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking, and note. 11/21/05 C T5A T5B Features Section - added Additive Phase Jitter bullet. 3.3V AC Characteristics Table - added Additive Phase Jitter. 3.3V AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter section. Updated Differential Input Clock Interface section. Updated Reliability Information. Updated format throughout the datasheet. 1/15/08 D T4C T5C Features Section - added mix voltage to supply voltage bullet. Added Mix DC Characteristics Power Supply Table. Added Mix AC Characteristics Table. Parameter Measurement Information Section - added 3.3V/2.5V LVCMOS Output Load AC Test Circuit diagram. Ordering Information Table - deleted ICS prefix from Part/Order Number column. 4/1/09 D T1 2 Output supply pins, Changed V DD to VDDO 11/1/12 D T8 15 Removed leaded orderable parts from Ordering Information table 11/14/12 D T8 15 Fixed typo: removed extra “I” from orderable part number. Updated Headers and Footers. Updated Contact information. 7/17/14 D Removed ICS from part number where needed. Updated data sheet header and footer. 3/30/16
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com 83948I-147 Data Sheet