83947i Datasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 10

Technical content

Low Skew, 1-to-9 LVCMOS Fanout Buffer 83947 Data Sheet ©2016 Integrated Device Technology, Inc Revision B March 17, 20161 GENERAL DESCRIPTION The 83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 byutilizing the ability of the outputs to drive two series terminated lines. Guaranteed output and part-to-part skew characteristics make the 83947I ideal for high performance, single ended applications that also require a limited output voltage. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

  • 9 LVCMOS/LVTTL outputs
  • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
  • Maximum output frequency: 110MHz
  • Output skew: 500ps (maximum)
  • Part-to-part skew: 2ns (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package available 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 GND V DDO GND V DDO GND GND CLK_SEL CLK0 CLK1 CLK_EN OE V DD GND GND V DDO GND V DDO GND GND VDDO GND VDDO GND ICS83947I

83947 Data Sheet

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE 24, 25, 29, 32 GND Power Power supply ground. selects CLK0. LVCMOS / LVTTL interface levels. 3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 10, 14, 18, 22, 27, 31 V DDO Power Output supply pins. Q3, Q2, Q1, Q0 Output Q0 thru Q8 clock outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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©2016 Integrated Device Technology, Inc Revision B March 17, 20163 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Coret Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Input Supply Current 33 50 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 3.6 V VIL Input Low Voltage 0.8 V IIN Input Current CLK0, CLK1, CLK_SEL, OE, CLK_EN -100 µA VOH Output High Voltage I OH = -20mA 2.5 V VOL Output Low Voltage I OL = 20mA 0.4 V ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.

©2016 Integrated Device Technology, Inc Revision B March 17, 20165 PARAMETER MEASUREMENT INFORMATION PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT SKEW PART-TO-PART SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision B March 17, 20169 REVISION HISTORY SHEET Rev Table Page Description of Change Date AT 5 4 AC Characterisitics Table, tS and tH rows- revised Test Conditions to read CLK_EN to CLK. 6/21/02 B Added Lead Free bullet in Features section. Pin Characteristics Table - changed CIN from 4pF max. to 4pF min. ROUT added 5Ω min and 12Ω max. Ordering Information Table - add Lead-Free part. Updated format throughout data sheet. 10/11/04 BT 8 8 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/9/10 BT 8 8 Updated datasheet format Ordering information - removed leaded part numbers - PDN CQ-13-02 expired 11/10/14 B Removed ICS from part number where needed. Updated header and footer. 3/17/16

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