ICS83947I-147 Datasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 12

Technical content

Low Skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer 83947I-147 Data Sheet ©2016 Integrated Device Technology, Inc Revision A March 18, 20161 GENERAL DESCRIPTION The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50  series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series terminated lines. Guaranteed output and part-to-part skew characteristics make the 83947I-147 ideal for high performance, 3.3V or 2.5V single ended applications. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

  • Nine LVCMOS/LVTTL outputs
  • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
  • Maximum output frequency: 250MHz
  • Output skew: 115ps (maximum)
  • Part-to-part skew: 500ps (maximum)
  • Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 GND V DDO GND V DDO GND GND CLK_SEL CLK0 CLK1 CLK_EN OE V DD GND GND V DDO GND V DDO GND GND VDDO GND VDDO GND ICS83947I-147

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE 24, 25, 29, 32 GND Power Power supply ground. selects CLK0. LVCMOS / LVTTL interface levels. 3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 10, 14, 18, 22, 27, 31 V DDO Power Output supply pins. Q3, Q2, Q1, Q0 Output Q0 thru Q8 clock outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 X Hi-Z

©2016 Integrated Device Technology, Inc Revision A March 18, 20163 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.0 3.3 3.6 V 2.375 2.5 2.625 V VDDO Output Supply Voltage 3.0 3.3 3.6 V 2.375 2.5 2.625 V IDD Input Supply Current 50 mA IDDO Output Supply Current 9m A ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage CLK0, CLK1 -0.3 1.3 V CLK_SEL, CLK_EN, OE -0.3 0.8 V IIH Input High Current CLK0, CLK1, OE, CLK_ SEL, CLK_EN VDD = VIN = 2.625V 5 µA IIL Input Low Current CLK0, CLK1, OE, CLK_ SEL, CLK_EN VDD = 32.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 1.8 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test Circuit Diagram. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 3.6 V VIL Input Low Voltage 0.8 V IIN Input Current CLK0, CLK1, OE, CLK_SEL, CLK_EN -100 µA VOH Output High Voltage; NOTE 1 I OH = -20mA 2.5 V VOL Output Low Voltage; NOTE 1 I OL = 20mA 0.4 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test Circuit Diagram.

©2016 Integrated Device Technology, Inc Revision A March 18, 20164 TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay, NOTE 1 f ≤ 250MHZ 2 4.2 ns tsk(o) Output Skew; NOTE 2, 5 Measured on rising edge @VDDO/2 115 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 Measured on rising edge @VDDO/2 500 ps tjit(Ø) Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section (12KHz to 20MHz) 0.2 ps t R / tF Output Rise/Fall Time 0.8V to 2.0V 0.2 1 ns tPW Output Pulse Width f > 133MHz t Period/2 - 1 t Period/2 + 1 ns odc Output Duty Cycle f ≤ 133MHz 40 60 % tEN Output Enable Time; NOTE 4 10 ns tDIS Output Disable Time; NOTE 4 10 ns tS Clock Enable Setup Time 0 ns tS Clock Enable Hold Time 1 ns All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay, NOTE 1 f ≤ 250MHZ 2.4 4.5 ns tsk(o) Output Skew; NOTE 2, 5 Measured on rising edge @VDDO/2 130 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 Measured on rising edge @VDDO/2 600 ps tjit(Ø) Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section (12KHz to 20MHz) 0.1 ps t R / tF Output Rise/Fall Time 20% - 80% 300 800 ps tPW Output Pulse Width t Period/2 - 1.2 t Period/2 + 1.2 ns tEN Output Enable Time; NOTE 4 10 ns tDIS Output Disable Time; NOTE 4 10 ns tS Clock Enable Setup Time 0 ns tS Clock Enable Hold Time 1 ns All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision A March 18, 20165 ADDITIVE PHASE JITTER The spectral purity in a band at a specifi c offset from the fun- damental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the As with most timing specifi cations, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. This is illustrated above. The 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. Additive Phase Jitter, RMS @ 156.25MHz (12KHz to 20MHz) = 0.01ps typical @ 2.5V -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ Additive Phase Jitter, RMS @ 156.25MHz (12KHz to 20MHz) = 0.02ps typical @ 3.3V

©2016 Integrated Device Technology, Inc Revision A March 18, 20166 PARAMETER MEASUREMENT INFORMATION 2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT SKEW 3.3V OUTPUT RISE/FALL TIME 2.5V OUTPUT RISE/FALL TIME

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A March 18, 201611 REVISION HISTORY SHEET Rev Table Page Description of Change Date AT 8 1 0 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/12/10 Deleted non lead-free ordering information. Deleted tape & reel count. 2/27/13 A Removed ICS from part numbers where needed. Updated header and footer. 3/18/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support