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Low Skew, 1-to-9 LVCMOS Fanout Buffer 83947 DATASHEET 83947 REVISION B NOVEMBER 10, 2014 1 ©2014 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 byutilizing the ability of the outputs to drive two series terminated lines. Guaranteed output and part-to-part skew characteristics make the ICS83947I ideal for high performance, single ended applications that also require a limited output voltage. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

  • 9 LVCMOS/LVTTL outputs
  • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
  • Maximum output frequency: 110MHz
  • Output skew: 500ps (maximum)
  • Part-to-part skew: 2ns (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package available 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 GND V DDO GND V DDO GND GND CLK_SEL CLK0 CLK1 CLK_EN OE V DD GND GND V DDO GND V DDO GND GND VDDO GND VDDO GND ICS83947I

83947 DATA SHEET

2 REVISION B 11/10/14

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE 24, 25, 29, 32 GND Power Power supply ground. selects CLK0. LVCMOS / LVTTL interface levels. 3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 10, 14, 18, 22, 27, 31 V DDO Power Output supply pins. Q3, Q2, Q1, Q0 Output Q0 thru Q8 clock outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 X Hi-Z

3 LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Coret Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Input Supply Current 33 50 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 3.6 V VIL Input Low Voltage 0.8 V IIN Input Current CLK0, CLK1, CLK_SEL, OE, CLK_EN -100 µA VOH Output High Voltage I OH = -20mA 2.5 V VOL Output Low Voltage I OL = 20mA 0.4 V ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

4 REVISION B 11/10/14

TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.

5 LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT SKEW PART-TO-PART SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT

6 REVISION B 11/10/14

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

7 LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER

TABLE 7. PACKAGE DIMENSIONS

8 REVISION B 11/10/14

TABLE 8. ORDERING INFORMATION

9 LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER

Rev Table Page Description of Change Date AT 5 4 AC Characterisitics Table, tS and tH rows- revised Test Conditions to read CLK_EN to CLK. 6/21/02 B Added Lead Free bullet in Features section. Pin Characteristics Table - changed CIN from 4pF max. to 4pF min. ROUT added 5Ω min and 12Ω max. Ordering Information Table - add Lead-Free part. Updated format throughout data sheet. 10/11/04 BT 8 8 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/9/10 BT 8 8 Updated datasheet format Ordering information - removed leaded part numbers - PDN CQ-13-02 expired 11/10/14

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved.