ICS83940I-01 Data Sheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 19
Technical content
Features
- Eighteen LVCMOS/LVTTL outputs, 23 typical output impedance
- Selectable LVCMOS_CLK or LVPECL clock inputs
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, SSTL
- LVCMOS_CLK supports the following input types: LVCMOS or LVTTL
- Maximum output frequency: 175MHz
- Additive phase jitter, RMS: 0.108ps (typical), 3.3V/3.3V
- Output skew: 115ps (maximum)
- Part-to-part skew: 800ps (maximum), 3.3V/3.3V
- Operating supply modes:
- Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DDO Q10 Q11 GND GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK V DD VDDO GND VDDO Q0Q17 Q16 Q14 Q15 GND Q13 Q12 VDDO CLK_SEL PCLK nPCLK LVCMOS_CLK Q[0:17] Pulldown Pulldown Pulldown Pullup/Pulldown 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Pin AssignmentBlock Diagram ICS83940I-01
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pulldown Inverting differential LVPECL clock input. VDD/2 default when left floating. 7V DD Power Power supply pin. 8, 16, 21, 29 V DDO Power Output supply pins. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 3 Rev A 3/27/15 83940I-01 DATA SHEET Function Tables Table 3A. Clock Select Function Table Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. Control Input Clock CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK PCLK nPCLK Q[0:17] 0 – 0 1 LOW Differential to Single-Ended Non-Inverting 0 – 1 0 HIGH Differential to Single-Ended Non-Inverting 0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting 0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting 0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting 0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting 1 0 – – LOW Single-Ended to Single-Ended Non-Inverting 1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting
Rev A 3/27/15 4 LOW SKEW, 1-TO-18 LVPEC L-TO-LVCMOS/LVTTL FANOUT BUFFER 83940I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C Table 4C. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 3.6V Inputs, VI -0.3V to VDD + 0.3V Outputs, VO -0.3V to VDDO + 0.3V Input Current, IIN ±20mA Package Thermal Impedance, JA 53.5C/W (0 mps) Storage Temperature, TSTG -40C to 125C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 26 mA IDDO Output Supply Current No Load 28 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 25 mA IDDO Output Supply Current No Load 26 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 26 mA IDDO Output Supply Current No Load 26 mA
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 5 Rev A 3/27/15 83940I-01 DATA SHEET NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram. Table 4E. LVPECL DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C NOTE 1: Common mode voltage is defined as VIH. Table 4F. LVPECL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C NOTE 1: Common mode voltage is defined as VIH. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK VDD = 3.3V or 2.5V 2 V DD + 0.3 V CLK_SEL VIL Input Low Voltage LVCMOS_CLK V DD = 3.3V or 2.5V -0.3 1.3 V CLK_SEL V DD = 3.3V or 2.5V -0.3 0.8 V IIH Input High Current CLK_SEL, LVCMOS_CLK VDD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK_SEL, LVCMOS_CLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VDDO = 3.465V 2.8 V VDDO = 2.625V 2.1 V VOL Output Low Voltage; NOTE 1 V DDO = 3.465V or 2.65V 0.55 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK, nPCLK V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current PCLK V DD = 3.465V or 2.625V, VIN = 0V -10 µA nPCLK V DD = 3.465V or 2.625V, VIN = 0V -150 µA IIN Input Current ±200 µA VPP Peak-to-Peak Input Voltage 500 1000 mV VCMR Common Mode Input Voltage; NOTE 1 V DD – 1.4 V DD – 0.6 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK, nPCLK V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current PCLK V DD = 3.465V or 2.625V, VIN = 0V -10 µA nPCLK V DD = 3.465V or 2.625V, VIN = 0V -150 µA IIN Input Current ±200 µA VPP Peak-to-Peak Input Voltage 300 1000 mV VCMR Common Mode Input Voltage; NOTE 1 V DD – 1.4 V DD – 0.6 V
Rev A 3/27/15 6 LOW SKEW, 1-TO-18 LVPEC L-TO-LVCMOS/LVTTL FANOUT BUFFER 83940I-01 DATA SHEET Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 150MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 175 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.6 3.0 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.8 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.3 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.2 ns tjit Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section PCLK, nPCLK 155.52MHz, Integration Range: 12kHz – 20MHz 0.145 ps LVCMOS_CLK 0.108 ps tsk(o) Output Skew; NOTE 3, 5 Measured on the Rising Edge @ VDDO/2 115 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.4 ns LVCMOS_CLK ƒ 150MHz 1.2 ns Part-to-Part Skew; NOTE 6 PCLK/nPCLK ƒ > 150MHz 1.7 ns LVCMOS_CLK ƒ > 150MHz 1.4 ns Part-to-Part Skew; NOTE 4, 5 PCLK/nPCLK Measured on the Rising Edge @ VDDO/2 975 ps LVCMOS_CLK 800 ps tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle ƒ 150MHz 45 55 %
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 7 Rev A 3/27/15 83940I-01 DATA SHEET Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 150MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output V DDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 175 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.7 3.2 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.7 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.4 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.3 ns tjit Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section PCLK, nPCLK 155.52MHz, Integration Range: 12kHz – 20MHz 0.199 ps LVCMOS_CLK 0.137 ps tsk(o) Output Skew; NOTE 3, 5 Measured on the Rising Edge @ V DDO/2 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.5 ns LVCMOS_CLK ƒ 150MHz 1.3 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 1.8 ns LVCMOS_CLK ƒ > 150MHz 1.5 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 975 ps LVCMOS_CLK 875 ps tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle ƒ 150MHz 45 55 %
Rev A 3/27/15 8 LOW SKEW, 1-TO-18 LVPEC L-TO-LVCMOS/LVTTL FANOUT BUFFER 83940I-01 DATA SHEET Table 5C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 150MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 175 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.2 3.8 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.5 3.2 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.5 3.7 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 2.0 3.6 ns tjit Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section PCLK, nPCLK 155.52MHz, Integration Range: 12kHz – 20MHz 0.323 ps LVCMOS_CLK 0.116 ps tsk(o) Output Skew; NOTE 3, 5 Measured on the Rising Edge @ VDDO/2 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 2.6 ns LVCMOS_CLK ƒ 150MHz 1.7 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 2.2 ns LVCMOS_CLK ƒ > 150MHz 1.7 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 1.2 ns LVCMOS_CLK 1n s tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle ƒ 150MHz 43 57 %
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 9 Rev A 3/27/15 83940I-01 DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator, “SMA 100A 9kHz – 6GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". 3.3V/3.3V, LVCMOS_CLK Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.108ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)
Rev A 3/27/15 10 LOW SKEW, 1-TO-18 LVPEC L-TO-LVCMOS/LVTTL FANOUT BUFFER 83940I-01 DATA SHEET Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Part-to-Part Skew 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit Differential Input Level Output Skew SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDD -1.25V±5% 1.25V±5% 2.05V±5% VDDO tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO VDD GND PCLK nPCLK V CMR Cross Points V PP tsk(o) VDDO VDDO Qx Qy
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 11 Rev A 3/27/15 83940I-01 DATA SHEET Parameter Measurement Information, continued Output Rise/Fall Time Propagation Delay Output Duty Cycle/Pulse Width/Period 20% 80% 80% 20% tR tF Q[0:17] nPCLK Q[0:17] PCLK tpLH VDDO VDD 2LVCMOS_CLK tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:17]
This section provides information on power dissipation and junction temperature for the ICS83940DI-01. Equations and example calculations are also provided. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 53.5°C/W per Table 6 below. Table 6. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
Table 7. JA vs. Air Flow Table for a 32 Lead LQFP
Table 8. Package Dimensions for 32 Lead LQFP
Rev A 3/27/15 17 LOW SKEW, 1-TO-18 LVPEC L-TO-LVCMOS/LVTTL FANOUT BUFFER 83940I-01 DATA SHEET
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 18 Rev A 3/27/15 83940I-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date Updated data sheet format. 3/27/15
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