ICS83940DI RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Renesas Electronics Corporation
- PDF pages: 17
Technical content
Features
- Eighteen LVCMOS/LVTTL outputs
- Selectable LVCMOS_CLK or LVPECL clock inputs
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
- LVCMOS_CLK supports the following input types: LVCMOS or LVTTL
- Maximum output frequency: 250MHz
- Output skew: 150ps (maximum)
- Part-to-part skew: 750ps (maximum)
- Operating supply modes:
- Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging
- For functional replacement part for 83940DKILF, use 87016i Pin Assignments
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View CLK_SEL PCLK nPCLK LVCMOS_CLK Q0:Q17 Pulldown Pulldown Pulldown Pullup/Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO VDD Q10 Q11 GND Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO VDDO GND ICS83940DI 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DD Q11 GND GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO GND VDDO Q0Q17 Q16 Q14 Q15 GND Q13 Q12 VDDO ICS83940DI Low Skew, 1 to 18 LVPECL to LVCMOS/LVTTL Fanout Buffer ICS83940DI Datasheet
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non- inverting differential LVPECL clock input. 7, 21 V DD Power Power supply pin. 8, 16, 29 V DDO Power Output supply pins. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
3©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Function Tables Table 3A. Clock Select Function Table Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. Control Input Clock CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK PCLK nPCLK Q[0:17] 0–01 L O W D i f f e r e n t i a l t o S i n g l e - E n d e d N o n - I n v e r t i n g 0–10 H I G H D i f f e r e n t i a l t o S i n g l e - E n d e d N o n - I n v e r t i n g 0–0 Biased; NOTE
1 LOW Single-Ended to Single-Ended Non-Inverting
0–1 Biased; NOTE
1 HIGH Single-Ended to Single-Ended Non-Inverting
0– Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting 0– Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting 10–– L O W S i n g l e - E n d e d t o S i n g l e - E n d e d N o n - I n v e r t i n g 11–– H I G H S i n g l e - E n d e d t o S i n g l e - E n d e d N o n - I n v e r t i n g
4©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Table 4B. DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Item Rating Supply Voltage, VDD 3.6V Inputs, VI -0.3V to VDD + 0.3V Outputs, VO -0.3V to VDDO + 0.3V Input Current, IIN ±20mA Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 2.4 V VOL Output Low Voltage I OL = 20mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 500 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.45 V DD – 0.6 V IDD Power Supply Current 25 mA Symbol Parameter Test Condition s Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 1.8 V VOL Output Low Voltage I OL = 20mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 300 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.4 V DD – 0.6 V IDD Power Supply Current 25 mA
5©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Table 4C. DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -12mA 1.8 V VOL Output Low Voltage I OL = 12mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 300 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.4 V DD – 0.6 V IDD Power Supply Current 25 mA
6©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.6 3.0 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.8 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.3 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.2 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on the Rising Edge at VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.4 ns LVCMOS_CLK ƒ 150MHz 1.2 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 1.7 ns LVCMOS_CLK ƒ > 150MHz 1.4 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge at VDDO/2 850 ps LVCMOS_CLK 750 ps tR / tF Output Rise/Fall Time 0.5V to 2.4V 0.3 1.1 ns odc Output Duty Cycle ƒ < 134MHz 45 50 55 % 134MHz ƒ 250MHz 40 50 60 %
7©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.7 3.2 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.7 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.4 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.3 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on the Rising Edge at VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.5 ns LVCMOS_CLK ƒ 150MHz 1.3 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 1.8 ns LVCMOS_CLK ƒ > 150MHz 1.5 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge at VDDO/2 850 ps LVCMOS_CLK 750 ps tR / tF Output Rise/Fall Time 0.5V to 1.8V 0.3 1.2 ns
8©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Table 5C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 200 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.2 3.8 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.5 3.2 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.5 3.7 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 2.0 3.6 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measur ed on the Rising Edge at VDDO/2 200 ps LVCMOS_CLK 200 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 2.6 ns LVCMOS_CLK ƒ 150MHz 1.7 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 2.2 ns LVCMOS_CLK ƒ > 150MHz 1.7 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measur ed on the Rising Edge at VDDO/2 1.2 ns LVCMOS_CLK 1.0 ns tR / tF Output Rise/Fall Time 0.5V to 1.8V 0.3 1.2 ns odc Output Duty Cycle ƒ < 166MHz 40 60 %
9©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Part-to-Part Skew 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit Differential Input Level Output Skew SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDD -1.25V±5% 1.25V±5% 2.05V±5% VDDO t sk(pp) VDDO VDDO Part 1 Part 2 Qx Qy SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO VDD GND PCLK nPCLK VCMR Cross Points V PP t sk(o) VDDO VDDO Qx Qy
10©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Parameter Measurement Information, continued 3.3V Output Rise/Fall Time Propagation Delay 2.5V Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period 0.5V 2.4V 2.4V 0.5V tR tF Q0:Q17 nPCLK Q0:Q17 PCLK tpLH VDDO VDD 2LVCMOS_CLK 0.5V 1.8V 1.8V 0.5V tR tF Q0:Q17 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q17
of pad pattern for the leads to avoid any shorts. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) resistor can be tied from the LVCMOS_CLK input to ground. protection. A 1k resistor can be used.
14©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Reliability Information Table 6A. JA vs. Air Flow Table for a 32 Lead LQFP Table 6B. JA vs. Air Flow Table for a 32 Lead VFQFN Transistor Count The transistor count for ICS83940DI is: 820 JA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/ W 42.1°C/W 39.4 °C/W JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 40.2°C/ W 35.1°C/W 31.5 °C/W
15©2020 Renesas Electronics Corporation January 7, 2020 ICS83940DI Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/us/en/document/psc/prg32-package-outline-70-x-70-mm-lqfp
Ordering Information
Table 8. Ordering Information
Revision History
Part/Order Number Marking Package Shipping Packaging Temperature 83940DYILF ICS83940DYIL “Lead-F ree” 32 Lead LQFP Tray -40 C to 85C 83940DYILFT ICS83940DYIL “Lead-Fr ee” 32 Lead LQFP Tape & Reel -40 C to 85C Date Description January 7, 2020 ▪ Removed Output Duty Cycle sp ecification from table 5B. ▪ Updated Output Duty Cycle specifications in table 5C. ▪ Removed 83940DKILF/T devices from Ordering Information table. ▪ Updated Package Outline Drawings section. ▪ Rebranded document to Renesas template. May 19, 2016 Product Discontinuation Notice - Last time buy expires May 6, 2017. (83940DKILF) PDN CQ-16-01. March 20, 2013 Deleted “PROPOSED” stamp. November 27, 2012 Removed leaded orderables from Ordering Information table. September 7, 2010 Pin Characteristics Table - R OUT error, typical spec deleted. Updated Wiring the Differential Input to Accept Single-Ended Levels. Updated 32 VFQFN Package Outline. August 13, 2009 Added 32 Lead VFQFN Pin Assignment. Added VFQFN Thermal Release Path section. Added 32 VFQFN Thermal Table. Added 32 Lead VFQFN Package and Dimensions Table. Ordering Information Table - added 32 Lead VFQFN ordering information. Converted datasheet format. February 21, 2007 Absolute Maximum Ratings - corrected Storage Temperature from “-40°C to 125°C” to “-65°C to 150°C”. November 27, 2006 Features Section - added Lead-Free bullet. Application Information Section - added Recommendations for Unused Input and Output Pins. Application Information Section - added LVPECL Clock Input Interface. Ordering Information Table - added Lead-Free part number, marking, and note. Updated datasheet format. December 12, 2002 Pin Characteristics table - changed ROUT 25 maximum to 28 maximum. Delete RPULLUP row. 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read Added LVTTL to title. Updated format.
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© Renesas Electronics Corporation Package Revision HistoryRev No.Date CreatedDescription00Initial releaseFeb 2, 201601New FormatJan. 22, 2020