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- PDF pages: 19
Technical content
Features
- Eighteen LVCMOS/LVTTL outputs
- Selectable LVCMOS_CLK or LVPECL clock inputs
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
- LVCMOS_CLK supports the following input types: LVCMOS or LVTTL
- Maximum output frequency: 250MHz
- Output skew: 150ps (maximum)
- Part-to-part skew: 750ps (maximum)
- Operating supply modes:
- Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging
- For functional replacement part for 83940DKILF use 87016i Pin Assignments
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View CLK_SEL PCLK nPCLK LVCMOS_CLK Q0:Q17 Pulldown Pulldown Pulldown Pullup/Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO VDD Q10 Q11 GND Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO VDDO GND ICS83940DI 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DD Q10 Q11 GND GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK V DD VDDO GND VDDO Q0Q17 Q16 Q14 Q15 GND Q13 Q12 VDDO ICS83940DI PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF)
ICS83940DYI REVISION C May 19, 2016 2 ©2016 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non- inverting differential LVPECL clock input. Pulldown Inverting differential LVPECL clock input. VDD/2 default when left floating. 7, 21 V DD Power Power supply pin. 8, 16, 29 V DDO Power Output supply pins. Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
ICS83940DYI REVISION C May 19, 2016 3 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Function Tables Table 3A. Clock Select Function Table Table 3B. Clock Input Function Table NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. Control Input Clock CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK PCLK nPCLK Q[0:17] 0–01 L O W D i f f e r e n t i a l t o S i n g l e - E n d e d N o n - I n v e r t i n g 0–10 H I G H D i f f e r e n t i a l t o S i n g l e - E n d e d N o n - I n v e r t i n g 0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting 0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting 0 – Biased; NOTE 1 0 HIGH Single-E nded to Single-Ended Inverting 0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting 10–– L O W S i n g l e - E n d e d t o S i n g l e - E n d e d N o n - I n v e r t i n g 11–– H I G H S i n g l e - E n d e d t o S i n g l e - E n d e d N o n - I n v e r t i n g
ICS83940DYI REVISION C May 19, 2016 4 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Table 4B. DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Item Rating Supply Voltage, VDD 3.6V Inputs, VI -0.3V to VDD + 0.3V Outputs, VO -0.3V to VDDO + 0.3V Input Current, IIN ±20mA Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 2.4 V VOL Output Low Voltage I OL = 20mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 500 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.45 V DD – 0.6 V IDD Power Supply Current 25 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 1.8 V VOL Output Low Voltage I OL = 20mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 300 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.4 V DD – 0.6 V IDD Power Supply Current 25 mA
ICS83940DYI REVISION C May 19, 2016 5 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 4C. DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -12mA 1.8 V VOL Output Low Voltage I OL = 12mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 1 PCLK, nPCLK 300 1000 mV VCMR Common Mode Input Voltage; NOTE 1, 2 PCLK, nPCLK VDD – 1.4 V DD – 0.6 V IDD Power Supply Current 25 mA
ICS83940DYI REVISION C May 19, 2016 6 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output V DDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.6 3.0 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.8 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.3 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.2 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.4 ns LVCMOS_CLK ƒ 150MHz 1.2 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 1.7 ns LVCMOS_CLK ƒ > 150MHz 1.4 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 850 ps LVCMOS_CLK 750 ps tR / tF Output Rise/Fall Time 0.5V to 2.4V 0.3 1.1 ns odc Output Duty Cycle ƒ < 134MHz 45 50 55 % 134MHz ƒ 250MHz 40 50 60 %
ICS83940DYI REVISION C May 19, 2016 7 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output V DDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.7 3.2 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.7 3.0 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.6 3.4 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 1.8 3.3 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 1.5 ns LVCMOS_CLK ƒ 150MHz 1.3 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 1.8 ns LVCMOS_CLK ƒ > 150MHz 1.5 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 850 ps LVCMOS_CLK 750 ps tR / tF Output Rise/Fall Time 0.5V to 1.8V 0.3 1.2 ns odc Output Duty Cycle ƒ < 134MHz 45 50 55 %
ICS83940DYI REVISION C May 19, 2016 8 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output V DDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 200 MHz tPLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ 150MHz 1.2 3.8 ns LVCMOS_CLK; NOTE 2, 5 ƒ 150MHz 1.5 3.2 ns Propagation Delay PCLK, nPCLK; NOTE 1, 5 ƒ > 150MHz 1.5 3.7 ns LVCMOS_CLK; NOTE 2, 5 ƒ > 150MHz 2.0 3.6 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 200 ps LVCMOS_CLK 200 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ 150MHz 2.6 ns LVCMOS_CLK ƒ 150MHz 1.7 ns Part-to-Part Skew; NOTE 6 PCLK, nPCLK ƒ > 150MHz 2.2 ns LVCMOS_CLK ƒ > 150MHz 1.7 ns Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on the Rising Edge @ VDDO/2 1.2 ns LVCMOS_CLK 1.0 ns tR / tF Output Rise/Fall Time 0.5V to 1.8V 0.3 1.2 ns odc Output Duty Cycle ƒ < 134MHz 45 55 %
ICS83940DYI REVISION C May 19, 2016 9 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Part-to-Part Skew 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit Differential Input Level Output Skew SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDD -1.25V±5% 1.25V±5% 2.05V±5% VDDO tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO VDD GND PCLK nPCLK V CMR Cross Points VPP tsk(o) VDDO VDDO Qx Qy
ICS83940DYI REVISION C May 19, 2016 10 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued 3.3V Output Rise/Fall Time Propagation Delay 2.5V Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period 0.5V 2.4V 2.4V 0.5V tR tF Q0:Q17 nPCLK Q0:Q17 PCLK tpLH VDDO VDD 2LVCMOS_CLK 0.5V 1.8V 1.8V 0.5V tR tF Q0:Q17 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q17
ICS83940DYI REVISION C May 19, 2016 13 ©2016 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) resistor can be tied from the LVCMOS_CLK input to ground. resistance is not required but can be added for additional protection.
ICS83940DYI REVISION C May 19, 2016 14 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Reliability Information Table 6A. JA vs. Air Flow Table for a 32 Lead LQFP Table 6B. JA vs. Air Flow Table for a 32 Lead VFQFN Transistor Count The transistor count for ICS83940DI is: 820 JA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 40.2°C/W 35.1°C/W 31.5°C/W
ICS83940DYI REVISION C May 19, 2016 15 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 7A. Package Dimensions for 32 Lead LQFP Reference Document: JEDEC Publication 95, MS-026 JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0° 7° ccc 0.10
ICS83940DYI REVISION C May 19, 2016 16 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN Table 7B. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 7B. To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR Anvil Singulation N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 00 . 0 5 A3 0.25 Ref. b 0.18 0.25 0.30 ND & NE 8 D & E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50
ICS83940DYI REVISION C May 19, 2016 17 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Ordering Information
Table 8. Ordering Information
ICS83940DYI REVISION C May 19, 2016 18 ©2016 Integrated Device Technology, Inc. ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change Date A T2 2 Pin Characteristics table - changed ROUT 25 maximum to 28 maximum. Delete RPULLUP row. 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read Added LVTTL to title. Updated format. 12/12/02 A Features Section - added Lead-Free bullet. Application Information Section - added Recommendations for Unused Input and Output Pins. Application Information Section - added LVPECL Clock Input Interface. Ordering Information Table - added Lead-Free part number, marking, and note. Updated datasheet format. 11/27/06 B T6B T7B Added 32 Lead VFQFN Pin Assignment. Added VFQFN Thermal Release Path section. Added 32 VFQFN Thermal Table. Added 32 Lead VFQFN Package and Dimensions Table. Ordering Information Table - added 32 Lead VFQFN ordering information. Converted datasheet format. 8/13/09 C T2 2 Pin Characteristics Table - R OUT error, typical spec deleted. Updated Wiring the Differential Input to Accept Single-Ended Levels. Updated 32 VFQFN Package Outline. 9/7/10 C T8 17 Removed leaded orderables from Ordering Information table 11/27/12 C 1, 14,16 Deleted “PROPOSED” stamp 3/20/13 C Product Discontinuation Notice - Last time buy expires May 6, 2017. (83940DKILF) PDN CQ-16-01 5/19/16
ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved.
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